Texas Instruments OMAP36 Series, Техническое справочное руководство

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Display Subsystem Register Manual
Bits Field Name Description Type Reset
2:1 LOADMODE Loading Mode for the Palette/Gamma Table RW 0x0
WR: EVSYNC or VFP
0x0: Palette/Gamma Table and data are loaded every frame.
0x1: Palette/Gamma Table to be loaded. Users set the bit
when the palette/gamma table has to be loaded. H/W
resets the bit when table has been loaded.
(
DISPC_GFX_ATTRIBUTES . GfxEnable has to be set
to 1).
0x2: Frame data only loaded every frame
0x3: Palette/Gamma Table and frame data loaded on first
frame then switch to 10 (H/W).
0 PIXELGATED Pixel Gated Enable (only for Active Matrix Display) RW 0
WR: VFP
0x0: Pixel clock always toggles (only in Active Matrix mode)
0x1: Pixel clock only toggles when there is valid data to
display. (only in Active Matrix mode)
Table 7-151. Register Call Summary for Register DISPC_CONFIG
Display Subsystem Environment
• Transaction Timing Diagrams : [0]
Display Subsystem Integration
• Autoidle Mode : [1]
• Wake-Up Mode : [2]
Display Subsystem Functional Description
• Normal Mode : [3] [4] [5] [6] [7] [8] [9] [10]
• Alpha Mode : [11] [12] [13] [14]
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [15]
• Graphics DMA Registers : [16] [17] [18]
• Graphics Layer Configuration Registers : [19]
• Video DMA Registers : [20] [21]
• Video Configuration Register : [22]
• LCD-Specific Control Registers : [23]
• LCD Timings : [24] [25] [26] [27] [28]
• LCD Overlay : [29] [30] [31]
• LCD Color Phase Rotation : [32]
• TV Set-Specific Control Registers : [33]
• Digital Overlay : [34] [35] [36]
Display Subsystem Use Cases and Tips
• Autoidle : [37]
Display Subsystem Register Manual
• Display Controller Register Mapping Summary : [38]
1835 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated