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IVA2.2 Subsystem Register Manual
Table 5-175. L1PMPPAk
Address Offset
0x0000 A600 + (0x4*k)
Physical address
0x0184 A600 + (0x4*k)
Instance
IVA2.2 GEMXMC
Description
L1P Memory Protection Attribute Register Addresses for the 16MB page number i
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
SX
SR
UX
UR
SW
UW
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
LOCAL
Reserved
Bits
Field Name
Description
Type
Reset
31:16
Reserved
Write 0s for future compatibility. Read returns 0.
RW
0x0000
15
AID5
0: ID 5 does not have access permission
RW
1
1: ID 5 has access permission
14
AID4
0: ID 4 does not have access permission
RW
1
1: ID 4 has access permission
13
AID3
0: ID 3 does not have access permission
RW
1
1: ID 3 has access permission
12
AID2
0: ID 2 does not have access permission
RW
1
1: ID 2 has access permission
11
AID1
0: ID 1 does not have access permission
RW
1
1: ID 1 has access permission
10
AID0
0: ID 0 does not have access permission
RW
1
1: ID 0 has access permission
9
AIDX
0: External access is not permitted
RW
1
1: External access is permitted
8
LOCAL
0: DSP megamodule access is not permitted
RW
1
1: DSP megamodule access is permitted
7:6
Reserved
Write 0s for future compatibility.
RW
0
Read returns 0.
5
SR
0: Supervisor Read access is not permitted
RW
1
1: Supervisor Read access is permitted
4
SW
0: Supervisor Write access is not permitted
RW
1
1: Supervisor Write access is permitted
3
SX
0: Supervisor eXecute access is not permitted
RW
1
1: Supervisor eXecute access is permitted
2
UR
0: User Read access is not permitted
RW
1
1: User Read access is permitted
1
UW
0: User Write access is not permitted
RW
1
1: User Write access is permitted
0
UX
0: User eXecute access is not permitted
RW
1
1: User eXecute access is permitted
Table 5-176. Register Call Summary for Register L1PMPPAk
IVA2.2 Subsystem Basic Programming Model
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:
IVA2.2 Subsystem Register Manual
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851
SWPU177N – December 2009 – Revised November 2010
IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...