Texas Instruments OMAP36 Series, Техническое справочное руководство

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Camera ISP Integration
Table 6-19. Camera ISP CSI2A and CSI2C Receiver Event Generation from PHY (continued)
Event Mask Description
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [17] Control error for lane 3
17] ERRCONTROL3 ERRCONTROL3
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [20] Lane 1 in ULPM
20] STATEULPM1 STATEULPM1
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [21] Lane 2 in ULPM
21] STATEULPM2 STATEULPM2
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [22] Lane 3 in ULPM
22] STATEULPM3 STATEULPM3
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [25] All active lanes are entering in ULPM.
25] STATEALLULPMENTER STATEALLULPMENTER
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [26] At least one active lane exited the ULPM.
26] STATEALLULPMEXIT STATEALLULPMEXIT
As the CSI2A and CSI2C receivers supports eight contexts, the CSI2_CTx_IRQSTATUS and
CSI2_CTx_IRQENABLE registers are present eight times (one time per context).
The events are generated only for the enabled context(s). Table 6-20 describes the CSI2A and CSI2C
receiver event generation through the CTx interrupt status and interrupt enable registers.
Table 6-20. Camera ISP CSI2A and CSI2C CTx Receiver Event Generation
Event Mask Description
CSI2_CTx_IRQSTATUS [0] FS_IRQ CSI2_CTx_IRQENABLE [0] FS_IRQ Frame start: This interrupt is triggered on the
detection of a frame-start synchronization code
into the CSI2 data stream.
CSI2_CTx_IRQSTATUS [1] FE_IRQ CSI2_CTx_IRQENABLE [1] FE_IRQ Frame end: This interrupt is triggered on the
detection of a frame-end synchronization code
into the CSI2 data stream.
CSI2_CTx_IRQSTATUS [2] LS_IRQ CSI2_CTx_IRQENABLE [2] LS_IRQ Line start: This interrupt is triggered on the
detection of a line-start synchronization code
into the CSI2 data stream.
CSI2_CTx_IRQSTATUS [3] LE_IRQ CSI2_CTx_IRQENABLE [3] LE_IRQ Line end: This interrupt is triggered on the
detection of a line-end synchronization code
into the CSI2 data stream.
CSI2_CTx_IRQSTATUS [5] CS_IRQ CSI2_CTx_IRQENABLE [5] CS_IRQ CS error: This interrupt is triggered upon
detection of a mismatch between the
transmitter and receiver checksums (payload).
CSI2_CTx_IRQSTATUS [6] CSI2_CTx_IRQENABLE [6] Frame counter reached: This interrupt is
FRAME_NUMBER_IRQ FRAME_NUMBER_IRQ triggered when the frame counter reaches its
programmable target value.
CSI2_CTx_IRQSTATUS [7] CSI2_CTx_IRQENABLE [7] Line number reached: The programmable line
LINE_NUMBER_IRQ LINE_NUMBER_IRQ number is received. The modulo feature can be
selected (
CSI2_CTx_CTRL1 .LINE_MODULO).
When selected, the interrupt is generated for
each line number multiple of the programmed
line number
(
CSI2_CTx_CTRL3 .LINE_NUMBER);
otherwise, the interrupt is generated only for
the line number.
CSI2_CTx_IRQSTATUS [8] CSI2_CTx_IRQENABLE [8] ECC was used to correct a 1-bit error (long
ECC_CORRECTION_IRQ ECC_CORRECTION_IRQ packets only).
1153 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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