Texas Instruments OMAP36 Series, Техническое справочное руководство

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HS I
2
C Environment
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• 3-phase write transmission: The 3-phase write transmission cycle (see (a) of Figure 17-14 ) is a full
write operation in which the master can write 1 byte of data to a specific slave(s). The 7-bit slave
address in the ID value identifies the specific slave that the master intends to access. The subaddress
identifies the register location of the specified slave. The write data contains 8-bit data that the master
intends to write over the content of this specific address. The ninth bit of each of the three phases is a
don't-care bit (X bit).
• 2-phase write transmission: The 2-phase write transmission cycle is followed by a 2-phase read
transmission cycle (see below). The purpose of issuing a 2-phase write transmission cycle (see (b) of
Figure 17-14 ) is to identify the subaddress of some specific slave from which the master intends to
read data for the following 2-phase read transmission cycle. The ninth bit of each phase is a don't-care
bit (X bit).
• 2-phase read transmission: Either a 3-phase or a 2-phase write transmission cycle must be asserted
ahead of a 2-phase read transmission cycle. The 2-phase read transmission cycle (see (c) of
Figure 17-14 ) has no ability to identify the subaddress. The 2-phase write transmission cycle contains
read data of 8 bits and a ninth don't-care bit or NA bit. The master must drive the NA bit at logical 1.
In each transmission type, phase 1 (the 7-bit slave address of the ID value) is asserted by the master
to identify the selected slave to which the data is read or written. Each slave has a unique 7-bit slave
address. The 7-bit slave address of the ID value comprises 7 bits, from bit 7 to bit 1, that can identify
up to 128 slaves. The eighth bit, bit 0, is the read/write selector bit that specifies the transmission
direction of the current cycle. A logical 0 represents a write cycle and a logical 1 represents a read
cycle. The ninth bit of phase 1 is a don't-care bit (X bit).
Phase 2 (subaddress/read data) is asserted by the master (subaddress) or the slave(s) (read data). A
phase 2 transmission asserted by the master identifies the subaddress of the slave(s) the master
intends to access. A phase 2 transmission asserted by the slave(s) indicates the read data that the
master will receive. The slave(s) recognize the subaddress of this read data according to the previous
3-phase or 2-phase write transmission cycle. The ninth bit is defined as a don't-care bit (X bit) when
the master asserts phase 2. The ninth bit is defined as an NA bit when the slave(s) asserts the phase
2 transmission. The master is responsible for a logical 1 during the period of the NA bit.
Phase 3 (write data) is asserted only by the master. This phase contains the data the master intends to
write to the slave(s). Because the master asserts the transmission, the ninth bit of the phase 3
transmission is defined as a don't-care bit (X bit).
NOTE: A HS I
2
C controller configured in SCCB mode can perform two operations:
• Writing a single byte to an SCCB slave device by using the 3-phase write transmission
cycle
• Reading a single byte from an SCCB slave device by using the 2-phase write
transmission cycle followed by the 2-phase read transmission cycle
17.2.3 HS I
2
C Communication With Power Chip(s)
The HS I
2
C controller I2C4 interfaces between the external power chip(s) for voltage control. This module
is always configured as an I
2
C master transmitter; it does not support the SCCB protocol. For a definition
of master transmitter mode, see Section 17.2.1.3.5 , HS I
2
C Master Transmitter Mode.
Figure 17-15 shows a typical connection between master transmitter HS I
2
C controller I2C4 of the device
and external power chip(s).
2778 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
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