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UART/IrDA/CIR Functional Description
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When an interrupt is generated, the interrupt identification register (UARTi. IIR_REG ) sets the
UARTi. IIR_REG [0] IT_PENDING bit to 0 to indicate that an interrupt is pending, and provides the type of
interrupt through UARTi. IIR_REG [5:1]. Table 19-33 summarizes the interrupt control functions.
Table 19-33. UART Mode Interrupts
IIR_REG [5:0] Priority Level Interrupt Type Interrupt Source Interrupt Reset Method
000001 None None None None
000110 1 Receiver line OE, FE, PE, or BI errors occur in FE, PE, BI: Read RHR_REG . OE: Read
status characters in the RX FIFO. LSR_REG .
001100 2 RX time-out Stale data in RX FIFO Read RHR_REG .
000100 2 RHR interrupt DRDY (data ready) (FIFO disable) Read RHR_REG until interrupt condition
disappears.
RX FIFO above trigger level (FIFO
enable)
000010 3 THR interrupt TFE ( THR_REG empty) (FIFO Write to THR_REG until interrupt
disable) condition disappears.
TX FIFO below trigger level (FIFO
enable)
000000 4 Modem status See the MSR_REG register. Read MSR_REG .
010000 5 XOFF Receive XOFF characters/special Receive XON character(s), if XOFF
interrupt/special character interrupt/read of IIR_REG , if special
character character interrupt.
interrupt
100000 6 CTS, RTS RTS pin or CTS pin change state Read IIR_REG .
from active (low) to inactive (high).
For the receiver-line status interrupt, the RX_FIFO_STS bit (UARTi. LSR_REG [7]) generates the interrupt.
For the XOFF interrupt, if an XOFF flow character detection caused the interrupt, the interrupt is cleared
by an XON flow character detection. If special character detection caused the interrupt, the interrupt is
cleared by a read of the UARTi.
IIR_REG register.
19.4.4.1.4.1 Wake-Up Interrupt
Wake-up interrupt is a special interrupt that is not designed the same way as other interrupts. This
interrupt is enabled when the UARTi.
SCR_REG [4] RX_CTS_WU_EN bit is set to 1. The UARTi. IIR_REG
register is not modified when it occurs; the UART3. SSR_REG [1] RX_CTS_WU_STS bit must be checked
to detect a wake-up event.
When a wake-up interrupt occurs, the only way to clear it is to reset the UARTi. SCR_REG [4]
RX_CTS_WU_EN bit. This bit must be re-enabled (set to 1) after the current wake-up interrupt event is
processed to detect the next incoming wake-up event.
19.4.4.2 IrDA Mode (UART3 Only)
19.4.4.2.1 IrDA Clock Generation: Baud Generator
The IrDA function contains a programmable baud generator and a set of fixed dividers that divide the
48-MHz clock input down to the expected baud rate.
Figure 19-32 shows the baud rate generator and associated controls.
2910 UART/IrDA/CIR SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated