Texas Instruments OMAP36 Series, Техническое справочное руководство

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UART/IrDA/CIR Register Manual
Table 19-107. SSR_REG
Address Offset 0x044
Physical Address
See Table 19-39 to Table 19-40
Description Supplementary status register
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
TX_FIFO_FULL
DMA_COUNTER_RST
RX_CTS_DSR_WAKE_UP_STS
Bits Field Name Description Type Reset
15:3 Reserved Read returns 0. R 0x00000000
2 DMA_COUNTER_RST DMA counter reset. RW 1
0x0: The DMA counter will not be reset if the
corresponding FIFO is reset (via FCR[1] or
FCR[2])
0x1: The DMA counter will be reset if corresponding
FIFO is reset (via FCR[1] or FCR[2]).
1 RX_CTS_DSR_WAKE_UP_STS Pin falling edge detection: Reset only when SCR_REG [4] R 0
is reset to 0.
0x0: No falling-edge event on RX, nCTS, and nDSR
0x1: A falling edge occurred on RX, nCTS, or nDSR.
0 TX_FIFO_FULL TX FIFO status. R 0
0x0: TX FIFO is not full.
0x1: TX FIFO is full.
Table 19-108. Register Call Summary for Register SSR_REG
UART/IrDA/CIR Functional Description
• FIFO Management : [0]
• Register Access Modes : [1] [2] [3]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [4] [5] [6] [7] [8] [9] [10] [11] [12]
• UART Mode : [13]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [14] [15]
• UART/IrDA/CIR Register Description : [16]
2965 SWPU177N – December 2009 – Revised November 2010 UART/IrDA/CIR
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