Texas Instruments OMAP36 Series, Техническое справочное руководство

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Public Version
UART/IrDA/CIR Register Manual
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Bits Field Name Description Type Reset
31:8 Reserved Read returns 0. R 0x000000
7 RX_TRIG_ RW 0
GRANU1
0x0: Disables the granularity of 1 for TRIGGER RX
level
0x1: Enables the granularity of 1 for TRIGGER RX
level
6 TX_TRIG_ RW 0
GRANU1
0x0: Disables the granularity of 1 for TRIGGER TX
level
0x1: Enables the granularity of 1 for trigger TX level
5 RESERVED Read returns 0. Write has no functional effect. R 0
4 RX_CTS_ RX CTS wake-up enable RW 0
WU_EN
0x0: Disables the WAKE UP interrupt and clears
SSR_REG [1]
0x1: Waits for a falling edge of pins RX, nCTS, or
nDSR to generate an interrupt
3 TX_EMPTY_ RW 0
CTL_IT
0x0: Normal mode for THR interrupt (see Table 19-33
for details about UART mode interrupts)
0x1: The THR interrupt is generated when TX FIFO
and TX shift register are empty.
2:1 DMA_MODE_2 Specifies the DMA mode valid if SCR_REG [0] = 1 RW 0x0
0x0: DMA mode 0 (no DMA)
0x1: DMA mode 1 (UARTi_DMA_TX,
UARTi_DMA_RX)
0x2: DMA mode 2 (UARTi_DMA_RX)
0x3: DMA mode 3 (UARTi_DMA_TX)
0 DMA_MODE_ RW 0
CTL
0x0: The DMA_MODE is set with FCR_REG [3].
0x1: The DMA_MODE is set with SCR_REG [2:1].
Table 19-106. Register Call Summary for Register SCR_REG
UART/IrDA/CIR Functional Description
• FIFO Management : [0]
• FIFO Trigger : [1] [2]
• FIFO DMA Mode Operation : [3] [4]
• Register Access Modes : [5] [6] [7] [8] [9] [10]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27]
[28]
• UART Mode : [29] [30]
• UART Mode Power Management : [31]
UART/IrDA/CIR Basic Programming Model
• Quick start : [32] [33] [34] [35] [36] [37] [38] [39]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [40] [41]
• UART/IrDA/CIR Register Description : [42] [43] [44] [45] [46] [47] [48] [49] [50] [51]
2964UART/IrDA/CIR SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated