Texas Instruments OMAP36 Series, Техническое справочное руководство

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General-Purpose Memory Controller
When RDACCESSTIME completes, control-signal timings are frozen during the multiple data transactions,
corresponding to PAGEBURSTACCESSTIME multiplied by the number of remaining data transactions.
• Chip-select signal nCS:
– nCS assertion time is controlled by the GPMC. GPMC_CONFIG2_i [3:0] CSONTIME field and
ensures the address setup time to nCS assertion.
– nCS deassertion time is controlled by the GPMC. GPMC_CONFIG2_i [12:8] CSRDOFFTIME field
and ensures the address hold time to nCS deassertion.
• Address valid signal nADV:
– nADV assertion time is controlled by the GPMC. GPMC_CONFIG3_i [3:0] ADVONTIME field.
– nADV deassertion time is controlled by the GPMC. GPMC_CONFIG3_i [12:8] ADVRDOFFTIME
field.
• Output enable signal nOE:
– nOE assertion indicates a read cycle.
– nOE assertion time is controlled by the GPMC. GPMC_CONFIG4_i [3:0] OEONTIME field.
– nOE deassertion time is controlled by the GPMC. GPMC_CONFIG4_i [12:8] OEOFFTIME field.
• Initial latency for the first read data is controlled by the RDACCESSTIME parameter.
The access time is defined in the GPMC.
GPMC_CONFIG5_i [20:16] RDACCESSTIME field.
During consecutive accesses, the GPMC increments the address after each data read completes.
• Delay between successive read data in the page is controlled by the PAGEBURSTACCESSTIME
parameter:
– This timing is defined in the GPMC. GPMC_CONFIG5_i [27:24] PAGEBURSTACCESSTIME field.
– Depending on the device page length, the GPMC can control device page crossing during a burst
request and insert initial RDACCESSTIME latency. Note that page crossing is only possible with a
new burst access, meaning a new initial access phase is initiated.
• Total access time (RDCYCLETIME) corresponds to RDACCESSTIME plus the address hold time
starting from the nCS deassertion plus the time from RDACCESSTIME to CSRDOFFTIME.
– The read cycle time is defined in the GPMC. GPMC_CONFIG5_i [4:0] RDCYCLETIME field.
– In Figure 10-14 , the RDCYCLETIME programmed value equals RDCYCLETIME0 (before paged
accesses) + RDCYCLETIME1 (after paged accesses).
• Direction signal DIR:
DIR goes from OUT to IN at the same time as nOE assertion time.
After a read operation, if no other access (read or write) is pending, the data bus is driven with the
previous read value. See
Section 10.1.5.3.10 , Bus Keeping Support.
10.1.5.10 Synchronous Access
In synchronous operations:
• The GPMC_CLK clock is provided outside the GPMC when accessing the memory device.
• The GPMC_CLK clock is derived from the GPMC_FCLK clock using the
GPMC.
GPMC_CONFIG1_i [1:0] GPMCFCLKDIVIDER field (where i = 0 to 7).
• The GPMC. GPMC_CONFIG1_i [26:25] CLKACTIVATIONTIME field specifies that the GPMC_CLK is
provided outside the GPMC 0, 1, or 2 GPMC_FCLK cycles after start access time until CycleTime
completes.
• When the GPMC is configured for synchronous mode, the GPMC_CLK signal (which is an output)
must also be set as an input (CONTROL.CONTROL_PADCONF_GPMC_NCS7[24] INPUTENABLE1 =
1). GPMC_CLK is looped back through the output and input buffers of the corresponding GPMC_CLK
pad at device boundary. The looped-back clock is used to synchronize the sampling of the memory
signals.
10.1.5.10.1 Synchronous Single Read
Figure 10-15 and Figure 10-16 show a synchronous single-read operation with GPMCFCLKDIVIDER
equal to 0 and 1, respectively.
2147 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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