Texas Instruments OMAP36 Series, Техническое справочное руководство

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Display Subsystem Register Manual
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PP_BUSY
RESERVED
MODE
VC_EN
BTA_EN
SOURCE
VC_BUSY
CS_TX_EN
RESERVED
ECC_TX_EN
MODE_SPEED
TX_FIFO_FULL
BTA_LONG_EN
BTA_SHORT_EN
DMA_TX_REQ_NB DMA_RX_REQ_NB
DMA_TX_THRESHOLD TX_FIFO_NOT_EMPTY
DMA_RX_THRESHOLD RX_FIFO_NOT_EMPTY
Bits Field Name Description Type Reset
31:30 RESERVED Write 0s for future compatibility. RW 0x0
Reads returns 0.
29:27 DMA_RX_REQ_NB Selection of the use of the DMA request (associated to RW 0x0
the RX FIFO)
0x0: DSI_DMA_REQ0 is selected
0x1: DSI_DMA_REQ1 is selected
0x2: DSI_DMA_REQ2 is selected
0x3: DSI_DMA_REQ3 is selected
0x4: No DMA req selected
26:24 DMA_RX_THRESHOLD Defines the threshold value for the DMA request RW 0x0
(associated to the RX FIFO)
0x0: 1x 32 bits
0x1: 2 x 32 bits
0x2: 4 x 32 bits
0x3: 8 x 32 bits
0x4: 16 x 32 bits
0x5: 32 x 32 bits
23:21 DMA_TX_REQ_NB Selection of the use of the DMA request (associated to RW 0x0
the TX FIFO)
0x0: DSI_DMA_REQ0 is selected
0x1: DSI_DMA_REQ1 is selected
0x2: DSI_DMA_REQ2 is selected
0x3: DSI_DMA_REQ3 is selected
0x4: No DMA req selected
20 RX_FIFO_NOT_EMPTY FIFO status in command mode. Otherwise, this bit can be R 0x0
ignored.
0x0: The RX FIFO is empty (the FIFO does not contain
any data for the VC)
0x1: The RX FIFO is not empty (the FIFO contains at
least one byte for the VC)
19:17 DMA_TX_THRESHOLD Defines the threshold value for the DMA request RW 0x0
(associated to the TX FIFO)
0x0: 1x 32 bits
0x1: 2 x 32 bits
0x2: 4 x 32 bits
0x3: 8 x 32 bits
0x4: 16 x 32 bits
0x5: 32 x 32 bits
16 TX_FIFO_FULL FIFO status in command mode. Otherwise, this bit can be R 0x0
ignored.
0x0: The TX FIFO is not full (the FIFO can accept at least
one more 32-bit value)
0x1: The TX FIFO is full
1943 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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