Texas Instruments OMAP36 Series, Техническое справочное руководство

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PRCM Register Manual
Table 3-338. PM_PREPWSTST_MPU
Address Offset 0x0000 00E8
Physical Address 0x4830 69E8 Instance MPU_PRM
Description This register provides a status on the MPU domain previous power state. It indicates the state entered
during the last sleep transition.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESERVED
LASTPOWERSTATEENTERED
LASTL2CACHESTATEENTERED
LASTLOGICL1CACHESTATEENTERED
Bits Field Name Description Type Reset
31:8 RESERVED Read returns 0. R 0x000000
7:6 LASTL2CACHESTATEENTERE Last L2 Cache memory state entered RW 0x0
D
0x0: L2 Cache memory was previously OFF
0x1: L2 Cache memory was previously in RETENTION
0x2: Reserved
0x3: L2 Cache memory was previously ON
5:3 RESERVED Read returns 0. R 0x0
2 LASTLOGICL1CACHESTATE Last logic and L1 Cache state entered RW 0x0
ENTERED
0x0: MPU domain logic and L1 Cache was previously
OFF
0x1: MPU domain logic and L1 Cache was previously ON
1:0 LASTPOWERSTATEENTERED Last power state entered RW 0x0
0x0: MPU domain was previously OFF
0x1: MPU domain was previously in RETENTION
0x2: MPU domain was previously INACTIVE
0x3: MPU domain was previously ON
Table 3-339. Register Call Summary for Register PM_PREPWSTST_MPU
PRCM Basic Programming Model
• PM_PREPWSTST_ <domain_name> (Previous Power State Status Register) : [0]
PRCM Register Manual
• MPU_PRM Registers Register Summary : [1]
3.8.2.5 CORE_PRM Registers
3.8.2.5.1 CORE_PRM Register Summary
575 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated