Texas Instruments OMAP36 Series, Техническое справочное руководство

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HDQ/1-Wire Basic Programming Model
The clock must not be shut off after the command/ address byte is sent; otherwise, the data is not
written to the slave.
HDQ. HDQ_INT_STATUS must be read to clear the interrupt condition.
2. Set the CLOCKENABLE bit HDQ. HDQ_CTRL_STATUS [5] to 0 to disable the clock.
Do not access the module registers after the software has put the module into power-down mode
except to write to the clock-enable bit to take the module out of power-down mode.
18.5.4.2 System Idle Mode
This section describes the steps to follow at the module level before enabling the idle mode at the system
level (for more information about the system power management scheme, see
Chapter 3 , Power, Reset,
and Clock Management.
As part of the L4 interconnect clock domain, the HDQ/1-Wire clocks can be cut at the PRCM level.
HDQ_FCLK can be cut if the EN_HDQ bit PRCM.CM_FCLKEN1_CORE [22] is set to 0 and no other
modules require CORE_12M_FCLK. The software must verify that no transfer is in progress.
In a read operation:
1. Wait for an RX-complete interrupt.
In a read operation, the transfer is completed when the RX-complete flag (RXCOMPLETE bit
HDQ.
HDQ_INT_STATUS [1]) generates an interrupt.
2. Read the HDQ. HDQ_INT_STATUS to clear the read-complete interrupt flag.
3. Read the HDQ. HDQ_RX_DATA to retrieve the read data.
4. The HDQ_ICLK can be shut off by entering the system idle mode.
In a write operation:
1. Wait for a TX-complete interrupt.
In a write operation, the transfer is completed when the TX-complete flag (TXCOMPLETE bit
HDQ.
HDQ_INT_STATUS [2]) generates an interrupt. The software must check whether the interrupt
was generated after the address/command byte was sent or after the data byte was sent. The clock
must not be shut off after the command/address byte is sent; otherwise, the data is not written to the
slave.
2. Read the HDQ. HDQ_INT_STATUS to clear the TX-complete interrupt flag.
3. The HDQ_ICLK can be shut off by entering the system idle mode.
Concerning HDQ_ICLK, two situations can occur:
•
The clock is no longer required and EN_HDQ bit PRCM.CM_ ICLKEN1_CORE[22] is set by software.
In this case, the clock is cut off, provided no other modules require it. Before setting the EN_HDQ bit,
the software must follow the steps described in this section.
• AUTO_HDQ bit PRCM.CM_AUTOIDLE1_CORE[22] is set. In this case, the software must verify that
all HDQ/1-Wire transfers are complete before enabling the L4 interconnect clock domain idle mode.
Otherwise, the HDQ/1-Wire has no way to prevent the clock from being cut, because no hardware
mechanism exists. The steps listed in this section must be verified before putting the L4 clock domain
into idle state.
2857 SWPU177N – December 2009 – Revised November 2010 HDQ/1-Wire
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