Texas Instruments OMAP36 Series, Техническое справочное руководство

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SDMA Functional Description
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11.4.8 Thread Budget Allocation
When several concurrent channels are latency critical and hardware synchronized, a specific latency
cannot be ensured until the target is served. This situation occurs when the concurrent channel number is
superior to the number of available threads.
NOTE: Four threads are available on the read port, and two threads are available on the write port.
For a hardware-synchronized transfer (memory to peripheral), a minimum bandwidth for a latency-critical
transfer must be ensured to avoid collisions between two hardware requests.
Because it is latency critical, the software user is responsible for the following:
•
Programming the synchronized channel as a high-priority channel
• Reserving one or several threads for high-priority channels
The proposed implementation is as follows (see Section 11.5.5 ):
Prevent the regular channel queue from exceeding more than a programmable (3, 2, or 1) number of
threads on the read port and no more than one thread on the write port. This number can be set on the
global register
DMA4_GCR [13:12].
The thread reservation is programmable for maximum use of thread resources for concurrent, low-priority
channel transfer. Programmability can also allow a partial throughput control by limiting in software the
number of concurrent outstanding requests that break the pipelining.
Depending on the DMA4_GCR [13:12] value, the following threadID on the read/write ports are reserved
for a high-priority channel:
Read port priority thread reservation:
•
DMA4_GCR [13:12] = 0x0 => No ThreadID is reserved for high-priority channels.
• DMA4_GCR [13:12] = 0x1 => Read ThreadID 0 is reserved for high-priority channels.
• DMA4_GCR [13:12] = 0x2 => Read ThreadID 0 and Read ThreadID 1 are reserved for high-priority
channels.
• DMA4_GCR [13:12] = 0x3 => Read ThreadID 0, Read ThreadID 1, and Read ThreadID 2 are reserved
for high-priority channels.
Write port priority thread reservation:
• DMA4_GCR [13:12] = 0x0 => No ThreadID is reserved for high-priority channels
• DMA4_GCR [13:12] = 0x1 => Write ThreadID 0 is reserved for high-priority channels.
• DMA4_GCR [13:12] = 0x2 => Write ThreadID 0 is reserved for high-priority channels.
• DMA4_GCR [13:12] = 0x3 => Write ThreadID 0 is reserved for high-priority channels.
Regardless whether or not the enabled channels are of high priority, only the setting of the
DMA4_GCR [13:12] value forces the thread reservation to these values. Set the appropriate value to avoid
losing threads using only regular channels.
To have an independent read and write priority context, a per-channel bit DMA4_CCRi [26] is added for
write priority, and the previous priority bit becomes read priority bit DMA4_CCRi [6].
NOTE: The device has one priority bit per logical channel, not one per port.
11.4.9 FIFO Budget Allocation
To avoid fully occupying the FIFO with a high-priority transfer while low-priority channels wait in the
arbitration queue, two separate FIFO budgets are specified: one for high-priority channels and one for
low-priority channels. This is defined in the
DMA4_GCR register, allowing the user to share the FIFO
budget between the low- and high-priority channels. The amount of the FIFO allocated by the low- and
high-priority channels is fixed by the value set in the
DMA4_GCR [15:14] HI_LO_FIFO_BUDGET field. The
maximum channel FIFO depth is limited by the HI_LO_FIFO_BUDGET field as follows:
If the channel is low priority:
2356 SDMA SWPU177N – December 2009 – Revised November 2010
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