Texas Instruments OMAP36 Series, Техническое справочное руководство

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HS I
2
C Integration
Table 17-9. HS I
2
C Interrupt Events (continued)
Event Supported Status Bit Mask Bit This Event Happens When:
Name Configuration
Mode
AERR I
2
C and SCCB I2Ci. I2C_STAT [7] I2Ci. I2C_IE [7] A write access to the I2Ci. I2C_DATA register by the LH
event modes AERR AERR_IE through the L4-Core interconnect is performed while the TX
FIFO is full or a read access to the I2Ci.
I2C_DATA register
by the LH through the L4-Core interconnect is performed
while the RX FIFO is empty. When the RX FIFO is empty,
the read of the RX FIFO returns the previous read data
value. When the TX FIFO is full, a write in the TX FIFO is
ignored.
BF event I
2
C and SCCB I2Ci. I2C_STAT [8] BF I2Ci. I2C_IE [8] The I
2
C bus becomes free (after a transfer is ended on the
modes BF_IE bus and a stop [P] condition is detected).
AAS I
2
C mode only I2Ci. I2C_STAT [9] I2Ci. I2C_IE [9] The module has recognized its own slave address or an
event AAS AAS_IE alternate Own Address, or a general call (all address bits
cleared to 0).
XUDF I
2
C and SCCB I2Ci. I2C_STAT [10] I2Ci. I2C_IE [10] The module has recognized a transmission underflow
event transmit mode XUDF XUDF_IE interrupt event.
ROVR I
2
C and SCCB I2Ci. I2C_STAT [11] I2Ci. I2C_IE [11] The module has recognized an overrun event on the
event receive mode ROVR ROVR_IE receiving line.
RDR I
2
C receive I2Ci. I2C_STAT [13] I2Ci. I2C_IE [13] The module is configured as a receiver, a stop (P)
event mode only RDR RDR_IE condition was received on the I
2
C bus, and the RX FIFO
level is below the threshold (I2Ci. I2C_BUF [13:8] RTRSH bit
field value + 1).
XDR I
2
C master I2Ci. I2C_STAT [14] I2Ci. I2C_IE [14] The module is configured as a master transmitter, the TX
event transmit mode XDR XDR_IE FIFO level is below the threshold (I2Ci. I2C_BUF [5:0]
only XTRSH bit field value + 1), and the amount of data still to
be transferred is less than this threshold.
When an interrupt request is generated, software must read the I2Ci. I2C_STAT register to check which
event caused the interrupt request generation, process accordingly, and acknowledge each processed
event by writing 1 to the corresponding bit in the I2Ci.
I2C_STAT register.
NOTE: The I2Ci. I2C_STAT [9] AAS status bit, corresponding to the AAS event, can be cleared in
two ways:
• If the I2Ci. I2C_IE [9] AAS_IE bit is set to 1 (interrupt generation enabled), the status bit is
cleared by writing 1 to the I2Ci. I2C_STAT [9] AAS status bit.
• If the I2Ci. I2C_IE [9] AAS_IE bit is cleared to 0 (interrupt generation disabled), the status
bit is cleared when a new start(S) or stop (P) condition is detected on the I
2
C bus.
2789 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
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