Texas Instruments OMAP36 Series, Техническое справочное руководство

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Table 6-18. Camera ISP CSI2A and CSI2C Receivers Event Generation (continued)
Event Mask Description
CSI2_IRQSTATUS [4] CONTEXT4 CSI2_IRQENABLE [4] CONTEXT4 At least one interrupt event enabled from Context
4 occurred (see
Table 6-20 ).
CSI2_IRQSTATUS [5] CONTEXT5 CSI2_IRQENABLE [5] CONTEXT5 At least one interrupt event enabled from Context
5 occurred (see
Table 6-20 ).
CSI2_IRQSTATUS [6] CONTEXT6 CSI2_IRQENABLE [6] CONTEXT6 At least one interrupt event enabled from Context
6 occurred (see
Table 6-20 ).
CSI2_IRQSTATUS [7] CONTEXT6 CSI2_IRQENABLE [7] CONTEXT7 At least one interrupt event enabled from Context
7 occurred (see
Table 6-20 ).
CSI2_IRQSTATUS [8] FIFO_OVF_IRQ CSI2_IRQENABLE [8] FIFO_OVF_IRQ FIFO overflow error: This interrupt is triggered on
detection of a FIFO overflow. An overflow can
occur if there is a mismatch between the data
input and output rates. A reset of the module is
required to restart correctly.
CSI2_IRQSTATUS [9] PHY_ERR_IRQ CSI2_IRQENABLE [9] PHT_ERR_IRQ Error signaling from PHY: This interrupt is
triggered when any error is received from the PHY
(events are defined in
CSI2_COMPLEXIO1_IRQSTATUS [see
Table 6-19 ]).
CSI2_IRQSTATUS [11] CSI2_IRQENABLE [11] ECC was not used to correct the header because
ECC_NO_CORRECTION_IRQ ECC_NO_CORRECTION_IRQ the error is larger than 1 bit (short and long
packets).
CSI2_IRQSTATUS [12] CSI2_IRQENABLE [12] ECC was used to correct a 1-bit error (short
ECC_CORRECTION_IRQ ECC_CORRECTION_IRQ packet only).
CSI2_IRQSTATUS [13] CSI2_IRQENABLE [13] Short packet reception (other than sync events:
SHORT_PACKET_IRQ SHORT_PACKET_IRQ line start, line end, frame start, and frame end;
only data types between 0x8 and 0xF are
considered).
CSI2_IRQSTATUS [14] CSI2_IRQENABLE [14] OCP_ERR_IRQ OCP error
OCP_ERR_IRQ
Table 6-19 shows CSI2A and CSI2C receiver event generation interrupt status and interrupt enable
registers receiving signals from the associated PHY.
Table 6-19. Camera ISP CSI2A and CSI2C Receiver Event Generation from PHY
Event Mask Description
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [0] Start of transmission error for lane 1
0] ERRSOTHS1 ERRSOTHS1
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [1] Start of transmission error for lane 2
1] ERRSOTHS2 ERRSOTHS2
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [2] Start of transmission error for lane 3
2] ERRSOTHS3 ERRSOTHS3
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [5] Start of transmission sync error for lane 1
5] ERRSOTSYNCHS1 ERRSOTSYNCHS1
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [6] Start of transmission sync error for lane 2
6] ERRSOTSYNCHS2 ERRSOTSYNCHS2
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [7] Start of transmission sync error for lane 3
7] ERRSOTSYNCHS3 ERRSOTSYNCHS3
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [10] Escape entry error for lane 1
10] ERRESC1 ERRESC1
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [11] Escape entry error for lane 2
11] ERRESC2 ERRESC2
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [12] Escape entry error for lane 3
12] ERRESC3 ERRESC3
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [15] Control error for lane 1
15] ERRCONTROL1 ERRCONTROL1
CSI2_COMPLEXIO1_IRQSTATUS [ CSI2_COMPLEXIO1_IRQENABLE [16] Control error for lane 2
16] ERRCONTROL2 ERRCONTROL2
1152Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
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