Texas Instruments OMAP36 Series, Техническое справочное руководство

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NOTE: Each serial line (line 1, line 2, and line 3) can be used as clock lane or data lane. All
polarities are supported. The MIPI DSI 1.0 protocol requires at least one clock line and one
data lane.
Lanes support four operating modes:
•
HS mode: High-speed transmit mode
• LP mode: Low-power transmit mode (also called low-power state [LPS])
• ULPS: Ultra-low power state used between two transmissions
• Off mode: Lane is off.
7.2.2.1.1 Data/Clock Configuration
From the device point of view, the DSI interface consists of six input/output signals representing three
differential signals: The serial clock and one or two serial data. The minimum configuration is one data pair
and one clock pair.
• The data signal carries the bit-serial data. The DSI transmitter in the host sends the data in-quadrature
with the DDR clock in high speed mode; otherwise, the clock is extracted from the received data in
low-speed mode. The data is transmitted byte-wise least significant bit (LSB) first.
• The clock signal carries the DDR clock signal in high speed transmission.
• Software users must configure the order of the data lanes to indicate the byte order while splitting the
byte stream for each DSI_PHY into bytes.
Table 7-9 details all the DSI lanes configuration.
Table 7-9. DSI Lane Configuration
Data/Clock Lane Position
DSI DSI_PHY Lane
Description
Configuration
1 2 3
Mode CLK + DATA1 CLK DATA1 Not used Single data lane
CLK Not used DATA1
DATA1 CLK Not used
Not used CLK DATA1
DATA1 Not used CLK
Not used DATA1 CLK
Mode CLK + DATA1 +
CLK DATA1 DATA2 Two data lanes
DATA2
CLK DATA2 DATA1
DATA1 CLK DATA2
DATA2 CLK DATA1
DATA1 DATA2 CLK
DATA2 DATA1 CLK
1586 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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