Texas Instruments OMAP36 Series, Техническое справочное руководство

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MMC/SD/SDIO Register Manual
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Table 24-34. MMC/SD/SDIO Register Summary (continued)
MMCHS1 MMCHS2
Register Width MMCHS3 Physical
Register Name Type Address Offset Physical Physical
(Bits) Address
Address Address
MMCHS_SYSTEST RW 32 0x0000 0028 0x4809 C028 0x480B 4028 0x480A D028
MMCHS_CON RW 32 0x0000 002C 0x4809 C02C 0x480B 402C 0x480A D02C
MMCHS_PWCNT RW 32 0x0000 0030 0x4809 C030 0x480B 4030 0x480A D030
MMCHS_BLK RW 32 0x0000 0104 0x4809 C104 0x480B 4104 0x480A D104
MMCHS_ARG RW 32 0x0000 0108 0x4809 C108 0x480B 4108 0x480A D108
MMCHS_CMD RW 32 0x0000 010C 0x4809 C10C 0x480B 410C 0x480A D10C
MMCHS_RSP10 R 32 0x0000 0110 0x4809 C110 0x480B 4110 0x480A D110
MMCHS_RSP32 R 32 0x0000 0114 0x4809 C114 0x480B 4114 0x480A D114
MMCHS_RSP54 R 32 0x0000 0118 0x4809 C118 0x480B 4118 0x480A D118
MMCHS_RSP76 R 32 0x0000 011C 0x4809 C11C 0x480B 411C 0x480A D11C
MMCHS_DATA RW 32 0x0000 0120 0x4809 C120 0x480B 4120 0x480A D120
MMCHS_PSTATE R 32 0x0000 0124 0x4809 C124 0x480B 4124 0x480A D124
MMCHS_HCTL RW 32 0x0000 0128 0x4809 C128 0x480B 4128 0x480A D128
MMCHS_SYSCTL RW 32 0x0000 012C 0x4809 C12C 0x480B 412C 0x480A D12C
MMCHS_STAT RW 32 0x0000 0130 0x4809 C130 0x480B 4130 0x480A D130
MMCHS_IE RW 32 0x0000 0134 0x4809 C134 0x480B 4134 0x480A D134
MMCHS_ISE RW 32 0x0000 0138 0x4809 C138 0x480B 4138 0x480A D138
MMCHS_AC12 R 32 0x0000 013C 0x4809 C13C 0x480B 413C 0x480A D13C
MMCHS_CAPA RW 32 0x0000 0140 0x4809 C140 0x480B 4140 0x480A D140
MMCHS_CUR_CAPA RW 32 0x0000 0148 0x4809 C148 0x480B 4148 0x480A D148
MMCHS_REV R 32 0x0000 01FC 0x4809 C1FC 0x480B 41FC 0x480A D1FC
24.7.2.2 MMCHS Registers
Table 24-35. MMCHS_SYSCONFIG
Address Offset 0x010
Physical Address 0x4809 C010 Instance MMCHS1
0x480A D010 MMCHS3
0x480B 4010 MMCHS2
Description System Configuration Register
This register allows controlling various parameters of the Interconnect interface.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Reserved
AUTOIDLE
SIDLEMODE SOFTRESET
ENAWAKEUP
CLOCKACTIVITY
Bits Field Name Description Type Reset
31:10 Reserved These bits are initialized to zero, and writes to them are ignored. R 0x00000
Reads return 0
9:8 CLOCKACTIVITY Clocks activity during wake up mode period. RW 0x0
Bit8: Interface clock
Bit9: Functional clock
3424 MMC/SD/SDIO Card Interface SWPU177N – December 2009 – Revised November 2010
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