Texas Instruments OMAP36 Series, Техническое справочное руководство

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IVA2.2 Subsystem Register Manual
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Table 5-482. SYSC_LICFG0
Address Offset 0x040
Physical address 0x01C2 0040 Instance IVA2.2 SYSC
Description This register controls various parameters of the IVA2.2 local interconnect network
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Reserved Reserved
Reserved Reserved
PAGEXINGEN
DMA2DOPTEN
GEMBURSTOPTEN
DMATRUECOMPEN
GEMTRUECOMPEN
Bits Field Name Description Type Reset
31:17 Reserved Write 0s for future compatibility. RW 0x0000
Read returns 0.
16 GEMBURSTOPTEN DSP megamodule cache-line operation transfers RW 0
optimizationcontrol:
0: DSP megamodule cache operation transfers are not
optimized
1: DSP megamodule cache operation transfers are
optimized
15 GEMTRUECOMPEN DSP megamodule program-initiated write-back transfer true RW 0
completion control:
0: DSP megamodule program-initiated write-back transfer
completion is not accurate
1: DSP megamodule program initiated write-back transfer
completion is accurate
14:10 Reserved Write 0s for future compatibility. RW 0x00
Read returns 0.
9 DMA2DOPTEN 2D transfers optimization control: RW 0
0: 2D DMA transfers optimization is disabled
1: 2D DMA transfers optimization is enabled
8 DMATRUECOMPEN DMA write transfer true completion control: RW 0
0: DMA write transfer completion is not accurate
1: DMA write transfer completion is accurate
7:4 Reserved Write 0xF for compatibilityRead returns 0xF RW 0xF
3:2 Reserved Write 0s for future compatibility. RW 0x0
Read returns 0.
1 PAGEXINGEN MMU page crossing enable: RW 0
0: Bursts are not allowed to cross 4KB page boundaries
1: Bursts are allowed to cross 4KB page boundaries
0 Reserved Write 0s for future compatibility. RW 0
Read returns 0.
Table 5-483. Register Call Summary for Register SYSC_LICFG0
IVA2.2 Subsystem Functional Description
• Interconnect Optimization : [0]
IVA2.2 Subsystem Basic Programming Model
• Coherence Maintenance : [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
• Prioritizing Defined Transfers : [11] [12] [13]
• Starting the Transfer : [14]
• Recommendations for Static Settings : [15] [16] [17] [18] [19] [20]
IVA2.2 Subsystem Register Manual
• SYSC Register Mapping Summary : [21]
982 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated