Texas Instruments OMAP36 Series, Техническое справочное руководство

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L3 Interconnect
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A check on the protection configuration confirms that this access was not allowed, either because the
initiator was not given write access or because the protection access parameters were not compatible with
the PM_OCMRAM.REQINFO_PERMISSIONS_0 settings.
A protection violation is not terminal from the interconnect point of view. If the module responsible for the
global chip protection do not reset the system (including the IVA2.2 subsystem and the OCM RAM), it
continues to run normally. A simple clearing of the error on both the IA and PM sides is required to return
to a clean status.
9.2.4.3.2 Acknowledging Errors
Time-out errors can never be acknowledged. To return to a normal operation after an error, the faulty
agent must be reset . An agent can be reset by asserting CORE_RESET bit
L3_IA_AGENT_CONTROL [0]
or L3_TA_AGENT_CONTROL [0], or by resetting the L3 interconnect through the PRCM.
Functional errors, including an in-band signal reporting a protection error, must be inactived through
software. Setting the INBAND_ERROR_PRIMARY and INBAND_ERROR_SECONDARY bits
L3_IA_AGENT_STATUS [28-29] in an IA, or setting the SERROR bit L3_IA_AGENT_STATUS [24] in a TA
clears the reported error. Table 9-31 lists the bit to clear and the associated type of error.
The L3_IA_ERROR_LOG or L3_TA_ERROR_LOG register must also be cleared by writing a nonzero
value simultaneously to the CODE bit field and the values currently stored in the MULTI and
SECONDARY fields.
Table 9-31. Error Clearing
Agent Type Error Register Field
Initiator In-band primary (application) error INBAND_ERROR_PRIMARY
In-band secondary (debug) error INBAND_ERROR_SECONDARY
Target Target asserts SError SERROR
The procedure to clear protection errors depends on the system protection configuration:
•
Write a nonzero value simultaneously into CODE bit field L3_PM_ERROR_LOG [27:24] and the value
currently stored in the MULTI bit L3_PM_ERROR_LOG [31] of the corresponding PM register block.
• Alternately, read either L3_PM_ERROR_CLEAR_SINGLE or L3_PM_ERROR_CLEAR_MULTI ,
depending on the current value of the MULTI field in the L3_PM_ERROR_LOG register. This solution,
which allows the clearing of protection errors without having a write access on other protection
registers, preserves protection.
L3_SI_FLAG_STATUS_0 or L3_SI_FLAG_STATUS_1 must be checked at the end of any error
acknowledging sequence to confirm that the acknowledgement was successful and that no other error is
pending.
9.2.4.4 Typical Example of Firewall Programming Example
All four regions in the IVA2.2 target firewall can be configured with no restrictions. However, protection is
required for a 14K-byte region starting at address 0x0 in address space 2, and it must accept any access
from any initiator for the rest of the target. The protection restricts allowed accesses as follows:
• Only the IVA2.2 and the MPU can read from this memory.
• Only the MPU can write to this memory.
• The protection parameters must include supervisor and functional.
Only accesses declared as supervisor and functional are allowed to pass through the protected region of
the firewall. There is no restriction on other attributes.
Table 9-32 lists the possible parameter combinations, whether they are allowed to pass or not, and why
they are rejected.
2024 Interconnect SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated