Texas Instruments OMAP36 Series, Техническое справочное руководство

Страница: 2384 / 3738

Public Version
SDMA Register Manual
www.ti.com
Bits Field Name Description Type Reset
15:14 HI_LO_FIFO_BUDGET Allow to have a separate Global FIFO budget for high RW 0x0
and low priority channels.
For Hi priority Channel:
(Per_channel_Maximum FIFO depth + 1) x Number of
active High priority Channel =< High Budget FIFO
For Low priority channel:
(Per_channel_Maximum FIFO depth + 1) x Number of
active Low priority Channel =< Low Budget FIFO
0x0: no fixed budget for neither higher nor lower priority
channel
0x1: 75% of FIFO for low priority and 25% for high priority
channels
0x2: 25% of FIFO for low priority and 75% for high priority
channels
0x3: 50% of FIFO for low priority and 50% for high priority
channels
13:12 HI_THREAD_ Allow thread reservation for high priority channel on both RW 0x0
RESERVED read and write ports.
0x0: No ThreadID is reserved on the Read Port for high
priority channels. No ThreadID is reserved on the Write
Port for high priority channels.
0x1: Read Port ThreadID 0 is reserved for high priority
channels. Write Port ThreadID 0 is reserved for high
priority channels.
0x2: Read port ThreadID 0 and ThreadID 1 are reserved
for high priority channels. Write Port ThreadID 0 is
reserved for high priority channels.
0x3: Read PortThreadID 0, ThreadID 1 and ThreadID 2
are reserved for high priority channels. Write Port
ThreadID 0 is reserved for high priority channels.
11:8 RESERVED Reserved. Write 0s for future compatibility. Read returns RW 0x0
0.
7:0 MAX_CHANNEL_ Maximum FIFO depth allocated to one logical channel. RW 0x10
FIFO_DEPTH Maximum FIFO depth can not be 0x0. It should be at
least 0x1 or greater. Note that If channel limit is less than
destination burst size enough data will not be
accumulated in the data FIFO and it will never be sent
out on the WR port. The burst size should be less than
the FIFO limit specified in this bit field.
Table 11-35. Register Call Summary for Register DMA4_GCR
SDMA Functional Description
• Logical Channel Transfer Overview : [0] [1] [2]
• FIFO Queue Memory Pool : [3]
• Thread Budget Allocation : [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
• FIFO Budget Allocation : [15] [16]
SDMA Basic Programming Model
• Setup Configuration : [17]
• Concurrent Software and Hardware Synchronization : [18] [19]
SDMA Register Manual
• SDMA Register Summary : [20]
2384 SDMA SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated