Texas Instruments OMAP36 Series, Техническое справочное руководство

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CLKG
FSG
1 2 3 4 5 6 7 8
9 10 11 12
13 14 15 16
17 18 19
Frame-sync pulse width: (FWID+1)× CLKG
Frame-sync period: (FPER+1)× CLKG
mcbsp-055
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McBSP Basic Programming Model
Figure 21-65. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
When the SRG comes out of reset, FSG is in its inactive state. Then, when GRST=1 and FSGM=1, a
frame-synchronization pulse is generated. The frame width value (FWID+1) is counted down on every
CLKG cycle until it reaches 0, at which time FSG goes low. At the same time, the frame period value
(FPER+1) is also counting down. When this value reaches 0, FSG goes high, indicating a new frame.
21.5.1.5.2.4 Clock Behavior
21.5.1.5.2.4.1 Set the receive clock mode
McBSPi. MCBSPLP_PCR_REG [8] CLKRM bit, McBSPi. MCBSPLP_SPCR1_REG [15] ALB bit and
McBSPi. MCBSPLP_XCCR_REG [5] DLB bit are used to set the receive clock mode.
Table 21-30 shows how to select various sources to provide the receive clock signal and affect the
mcbsp_clkr pin. The McBSPi. MCBSPLP_PCR_REG [0] CLKRP bit determines the polarity of the signal on
the mcbsp_clkr pin.
Table 21-30. CLKRM Effect on Receive Clock Signal and mcbsp_clkr Pin
CLKRM Source of Receive Clock mcbsp_clkr Pin Status
0 The mcbsp_clkr pin is an input driven by an Input
external clock. The external clock signal is inverted
as determined by CLKRP bit before being used.
1 The SRG clock (CLKG) drives internal CLKR. Output. CLKG, inverted as determined by CLKRP, is driven
out on the mcbsp_clkr pin.
In the digital loop-back mode (DLB=1) or analog loop-back mode (ALB = 1), the transmit clock signal is
used as the receive clock signal. For more details on clock configuration, see
Section 21.4.3.1 .
21.5.1.5.2.4.2 Set the Receive Clock Polarity
McBSPi. MCBSPLP_PCR_REG [0] CLKRP bit is used to set the receive clock polarity.
The receive clock polarity bit, CLKRP, sets the edge used to sample received data. The receive data is
always sampled on the falling edge of internal CLKR. Therefore, if CLKRP=1 and external clocking is
selected (CLKRM=0 and CLKR is an input pin), the external rising–edge triggered input clock on CLKR is
inverted to a falling–edge triggered clock before being sent to the receiver. If CLKRP=1 and internal
clocking is selected (CLKRM=1), the internal falling–edge triggered clock is inverted to a rising–edge
triggered clock before being sent out on the mcbsp_clkr pin.
NOTE: CLKRP=CLKXP in a system where the same clock (internal or external) is used to clock the
receiver and transmitter. The receiver uses the opposite edge as the transmitter to ensure
valid setup and hold of data around this edge.
21.5.1.5.2.4.3 Set the SRG Clock Divide-Down Value
McBSPi. MCBSPLP_SRGR1_REG [7:0] CLKGDV bit field is used to set the SRG clock divide-down value.
3141 SWPU177N – December 2009 – Revised November 2010 Multi-Channel Buffered Serial Port
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