Public Version
SDRAM Controller (SDRC) Subsystem
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Table 10-167. SDRC_DLLA_CTRL
Address Offset
0x0000 0060
Physical Address
0x6D00 0060
Instance
SDRC
Description
This register controls the SDRC DLL A resource used for fine timing tuning on a double-data-rate
interface.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
FIXEDDELAY
MODEFIXEDDELAYINITLAT
RESERVED
ENADLL
DLLIDLE
LOCKDLL
RESERVED
RESERVED
RESERVED
DLLMODEONIDLEREQ
Bits
Field Name
Description
Type
Reset
31:24
FIXEDDELAY
Phase offset value in ModeFixedDelay mode. Maximum
RW
0x00
frequency supported in this mode is 83 MHz. FIXEDDELAY
steps are defined after DLL cell characterization.
23:16
MODEFIXEDDELAYINITLAT
Initial latency before first request to be processed in
RW
0x00
ModeFixedDelay mode
(1)
0x0: no initial latency before first access
0x1: 2 clock cycles before first access
0x2: 4 clock cycles before first access
0x3: 6 clock cycles before first access
0x4 : 8 clock cycles before first access
...
0xFF: 510 clock cycles before first access
15:8
RESERVED
Write 0s for future compatibility. Read returns 0.
RW
0x00
7
RESERVED
Reserved
RW
0x0
6:5
DLLMODEONIDLEREQ
Selects the DLL mode upon hardware idle request
RW
0x0
0x0: DLL in Power-down mode upon hardware idle request
0x1: DLL in DLL idle mode upon hardware idle request
0x2: No action upon hardware idle request. Input clock
frequency must not be changed.
0x3: Reserved for future use (no action upon hardware idle
request).
4
DLLIDLE
Enables the DLL Idle mode
RW
0x0
0x0: DLL Idle mode disabled
0x1: DLL Idle mode enabled
3
ENADLL
Enables DLL
RW
0x0
0x0: DLL disabled
0x1: DLL enabled
2
LOCKDLL
Selects the DLL functionality between the TrackingDelay mode
RW
0x0
(previously called lock mode) or the ModeFixedDelay mode
(previously called unlock mode). The DLL mode is updated in
the DLL cell after:
- DLLIDLE mode
- DLL power-down mode
0x0: LOCKDLL at 0 puts the DLL in TrackingDelay mode
(tracking counter started).
0x1: LOCKDLL at 1 puts the DLL in ModeFixedDelay mode. The
fixed delay defined in FIXEDDELAY bit field is used to delay
DQS lines for read accesses.
(1)
The DLL characterization shows that this feature is not useful and that this value must be left at 0x0.
2320
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
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Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
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