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High-Speed USB Host Subsystem
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NOTE:
• The PRCM USBHOST_48M_FCLK output is cut at PRCM level assuming all the
modules that share it have been disabled in the corresponding register. Disabling the
high-speed USB host controller is a necessary but not sufficient condition.
• The PRCM USBHOST_120M_FCLK output is cut at PRCM level assuming all the
modules that share it have been disabled in the corresponding register. Disabling the
high-speed USB host controller is a necessary but not sufficient condition.
• The PRCM USBHOST_L3_ICLK output is cut at PRCM level assuming all the modules
that share it have been disabled in the corresponding register. Disabling the high-speed
USB host controller is a necessary but not sufficient condition.
• The PRCM.CM_AUTOIDLE_USBHOST[0] AUTO_USBHOST bit is used to link/unlink
the high-speed USB host controller from USBHOST_L3_ICLK-related clock domain
transitions.
• For further details about source clocks gating and domain transitions, see Chapter 3 ,
Power, Reset, and Clock Management.
22.2.3.1.3.1.2 L3 Master Interface Power Management
The high-speed USB host controller can go to standby mode, in which case it stops generating
transactions on the interconnect. The module standby leads the PRCM to disable the USB clocks to save
power.
The high-speed USB host controller has a MSTANDBY/WAIT handshake mechanism with the PRCM
module (see
Figure 22-30 ).
The module is ready to enter standby mode (indicated by the MSTANDBY signal to the PRCM asserted)
when there is no USB activity and the module is idle. It means the following:
• The module is committed not to start any new transaction on its master interface.
• The whole module is idle and, therefore, the power manager can start the procedure to turn off the
interface clock, if needed. This procedure must be implemented using the slave power-management
protocol.
The handshake mechanism lets the module go to standby mode based on the
USBHOST.
UHH_SYSCONFIG [13:12] MIDLEMODE field.
Table 22-38. High-Speed USB Host Controller MIDLEMODE Settings
MIDLEMODE Selected Description
Value Mode
0x0 Force- The high-speed USB host controller enters standby mode unconditionally (MSTANDBY is asserted
standby unconditionally).
0x1 No-standby The high-speed USB host controller never enters standby mode (MSTANDBY is never asserted).
0x2 Smart- The high-speed USB host controller is ready to enter standby mode (MSTANDBY is asserted) when
standby there is no more activity on the USB master interface of the interconnect. MSTANDBY is asserted
when the module is idle and deasserted when the module is activated by either an external USB
event or an appropriate register access. The module then waits for MWAIT deassertion before a
DMA transfer is started.
22.2.3.1.3.1.3 L4 Slave Interface Power Management
At PRCM level, when all the conditions to shut off the high-speed USB host controller output clocks are
met (see
Chapter 3 , Power, Reset, and Clock Management for details), the PRCM module automatically
launches a hardware handshake protocol to ensure the high-speed USB host controller is ready to have
its clocks switched off. Namely, the PRCM asserts an IDLE request to the high-speed USB host controller.
Although this handshake is completely hardware and out of any software control, the way in which the
high-speed USB host controller acknowledges the PRCM IDLE request is configurable through the
USBHOST.
UHH_SYSCONFIG [4:3] SIDLEMODE bit field. Table 22-39 details SIDLEMODE settings and
the related acknowledgment modes.
3266 High-Speed USB Host Subsystem and High-Speed USB OTG Controller SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated