DATA[15:0]
WAIT
Data
OEOFFTIME
RDCYCLETIME
OEONTIME=0
CSRDOFFTIME = RDCYCLETIME
CSONTIME=0
RDACCESSTIME
nBE0/CLE
nCS
nOE/nRE
nADV/ALE
gpmc-024
Public Version
General-Purpose Memory Controller
www.ti.com
NOTE:
ALE is shared with the nADV output signal and has an inverted polarity from ADV. The
NAND qualifier deals with this. During the asynchronous NAND data access cycle, ALE is
kept stable.
10.1.5.14.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
NAND device data read and write accesses are achieved through a read or write request to the
chip-select-associated memory region at any address location in the region or through a read or write
request to the GPMC.
location (i = 0 to 7) mapped in the chip-select-associated
control register region. GPMC.
is not a true register, but an address location to
enable nRE or nWE signal control. The associated chip-select signal timing control must be programmed
according to the NAND device timing specification.
Reading data from the GPMC.
location or from any location in the associated
chip-select memory region activates an asynchronous read access.
•
nCS is controlled by the CSONTIME and CSRDOFFTIME timing parameters.
•
nRE is controlled by the OEONTIME and OEOFFTIME timing parameters.
•
To take advantage of nRE high-to-data invalid minimum timing value, the RDACCESSTIME can be set
so that data are effectively captured after nRE deassertion. This allows optimization of NAND read
access cycle time completion. For optimal timing parameter settings, see the NAND device and device
IC timing parameters.
ALE, CLE, and nWE are maintained inactive.
shows the NAND data read cycle.
Figure 10-24. NAND Data Read Cycle
Writing data to the GPMC.
location or to any location in the associated chip-select
memory region activates an asynchronous write access.
•
nCS is controlled by the CSONTIME and CSWROFFTIME timing parameters.
•
nWE is controlled by the WEONTIME and WEOFFTIME timing parameters.
•
ALE, CLE, and nRE (nOE) are maintained inactive.
shows the NAND data write cycle.
2160
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
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Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...