Texas Instruments OMAP36 Series, Техническое справочное руководство

Страница: 1958 / 3738

Public Version
Display Subsystem Register Manual
www.ti.com
Bits Field Name Description Type Reset
0x0: No reset
0x1: Reset done for the TXCLKESC domain for lane 1
24 RESETDONETXCLK RESETDONETXCLKESC0 R 0
ESC0
0x0: No reset
0x1: Reset done for the TXCLKESC domain for lane 0
23:0 RESERVED Read-only register. Read returns 0. R 0x000000
Table 7-445. Register Call Summary for Register DSI_PHY_REGISTER5
Display Subsystem Basic Programming Model
• Reset-Done Bits : [0] [1] [2] [3] [4] [5] [6]
Display Subsystem Register Manual
• DSI_PHY Register Mapping Summary : [7]
7.7.2.7 DSI PLL Control Module Registers
Table 7-446. DSI_PLL_CONTROL
Address Offset 0x0000 0000
Physical Address 0x4804 FF00 Instance DSI_PLL_CTRL
Description This register controls the PLL reset/power and modes
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
DSI_PLL_SYSRESET
DSI_PLL_HALTMODE
DSI_PLL_GATEMODE DSI_PLL_AUTOMODE
DSI_HSDIV_SYSRESET
Bits Field Name Description Type Reset
31:5 RESERVED Reserved. Write only zero for future compatibility. Reads return R 0x0000000
zero.
4 DSI_HSDIV_SYSRESET Force HSDIVIDER SYSRESET RW 0x0
0x0: HSDIVIDER SYSRESET controlled by power FSM
0x1: HSDIVIDER SYSRESET forced active
3 DSI_PLL_SYSRESET Force ADPLLM SYSRESET RW 0x0
0x0: PLL SYSRESET controlled by power FSM
0x1: PLL SYSRESET forced active
2 DSI_PLL_HALTMODE Allow PLL to be halted if no activity RW 0x0
0x0: PLL will not be halted
0x1: PLL will be halted based on activity
1 DSI_PLL_GATEMODE Allow PLL clock gating for power saving RW 0x0
0x0: CLKIN4DDR on
0x1: CLKIN4DDR gated by DSI Protocol Engine activity
1958 Display Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated