Texas Instruments OMAP36 Series, Техническое справочное руководство

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UART/IrDA/CIR Register Manual
Table 19-75. XOFF2_REG
Address Offset 0x01C
Physical Address
See Table 19-39 to Table 19-40
Description UART mode XOFF2 character.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED XOFF_WORD2
Bits Field Name Description Type Reset
31:8 Reserved Read returns 0. R 0x000000
7:0 XOFF_WORD2 Stores the 8-bit XOFF2 character used in UART modes RW 0x00
Table 19-76. Register Call Summary for Register XOFF2_REG
UART/IrDA/CIR Functional Description
• Register Access Modes : [0] [1]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [2] [3]
UART/IrDA/CIR Basic Programming Model
• Hardware and Software Flow Control Configuration : [4] [5] [6]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [7] [8]
Table 19-77. TLR_REG
Address Offset 0x01C
Physical Address
See Table 19-39 to Table 19-40
Description Trigger level register.
Stores the programmable transmit and receive FIFO trigger levels used for DMA and IRQ generation
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
TX_FIFO_TRIG_DMA
RX_FIFO_TRIG_DMA
Bits Field Name Description Type Reset
31:8 Reserved Read returns 0x00. R 0x000000
7:4 RX_FIFO_TRIG_ DMA Receive FIFO trigger level RW 0x0
3:0 TX_FIFO_TRIG_ DMA Transmit FIFO trigger level RW 0x0
2951 SWPU177N – December 2009 – Revised November 2010 UART/IrDA/CIR
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