Texas Instruments OMAP36 Series, Техническое справочное руководство

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Display Subsystem Register Manual
Table 7-270. RFBI_CYCLE_TIMEi
Address Offset 0x68+ (i* 0x18) Index i = 0 to 1
Physical address 0x4805 0868+ (i* 0x18) Instance RFBI
Description The control register allows configuration of the RFBI timing.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved ACCESSTIME CSPULSEWIDTH RECYCLETIME WECYCLETIME
RRENABLE
WRENABLE RWENABLE
WWENABLE
Bits Field Name Description Type Reset
31:28 Reserved Write 0s for future compatibility RW 0x0
Read returns 0
27:22 ACCESSTIME Access Time RW 0x00
Number of L4Clk cycles
21 WRENABLE Write to Read Pulse Width Enable (same CS) RW 0
0: CSPulseWidth does not apply on Write to Read access
1: CSPulseWidth applies on Write to Read access
20 WWENABLE Write to Write Pulse Width Enable (same CS) RW 0
0: CSPulseWidth does not apply on Write to Write access
1: CSPulseWidth applies on Write to Write access
19 RRENABLE Read to Read Pulse Width Enable (same CS) RW 0
0: CSPulseWidth does not apply on Read to Read access
1: CSPulseWidth applies on Read to Read access
18 RWENABLE Read to Write Pulse Width Enable (same CS) RW 0
0: CSPulseWidth does not apply on Read to Write access
1: CSPulseWidth applies on Read to Write access
17:12 CSPULSEWIDTH CS Pulse Width RW 0x00
Number of L4Clk cycles
11:6 RECYCLETIME RE Cycle Time RW 0x00
Number of L4Clk cycles
5:0 WECYCLETIME WE Cycle Time RW 0x00
Number of L4Clk cycles
Table 7-271. Register Call Summary for Register RFBI_CYCLE_TIMEi
Display Subsystem Environment
• Transaction Timing Diagrams : [0] [1] [2]
Display Subsystem Basic Programming Model
• RFBI Timings : [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
Display Subsystem Register Manual
• RFBI Register Mapping Summary : [16]
1877 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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