Texas Instruments OMAP36 Series, Техническое справочное руководство

Страница: 1578 / 3738

DISPC_FCLK
DISPC_PCLK
DISPC_DATA_STALL
DISPC_LCD_DATA[23:0]
DISPC_CLK_cycles_for_assertion
1_DISPC_CLK_cycle_for_de_assertion
PIXELS 1 PIXELS 2 PIXELS 3
dss-135
L4_CLK
RFBI_A0(D/C)
RFBI_CSi
RFBI_WR
RFBI_DA[15:0]
DATA0 DATA1
CSOnTime
WEOnTime
WEOffTime
WECycleTime
CSOffTime
CSOnTime
WECycleTime
(with i = 0, 1)
dss-012
Public Version
Display Subsystem Environment
www.ti.com
Figure 7-13. RFBI Data Stall Signal Diagram With Handcheck
– RFBI timing diagrams
Table 7-6 lists the programmable timing fields. Figure 7-14 through Figure 7-16 show timing diagrams
of read/write transactions to the LCD panel for the RFBI mode.
Table 7-6. Programmable Timing Fields in RFBI Mode
Timing Name Register Field Description
CSOnTime DSS. RFBI_ONOFF_TIMEi [3:0] CS assertion time from start access time
CSONTIME (with I = 0 or 1)
CSOffTime DSS. RFBI_ONOFF_TIMEi [9:4] CS deassertion time from start access time
CSOFFTIME (with I = 0 or 1)
WeCycleTime DSS. RFBI_CYCLE_TIMEi [5:0] The time when A0 becomes valid until write cycle
WECYCLETIME (with I = 0 or 1) completion
WEOnTime DSS_RFBI_ONOFF_TIMEi[13:10] WE assertion delay time from start access time
WEONTIME (with I = 0 or 1)
WEOffTime DSS_RFBI_ONOFF_TIMEi[19:14] WE deassertion delay time from start access time
WEOFFTIME (with I = 0 or 1)
RECycleTime DSS. RFBI_CYCLE_TIMEi [11:6] The time when A0 becomes valid until read cycle
RECYCLETIME (with I = 0 or 1) completion
REOnTime DSS_RFBI_ONOFF_TIMEi[23:20] RE assertion delay time from start access time
REONTIME (with I = 0 or 1)
REOffTime DSS. RFBI_ONOFF_TIMEi [29:24] RE assertion delay time from start access time
REOFFTIME (with I = 0 or 1)
CSPulseWidth DSS. RFBI_CYCLE_TIMEi [17:12] The time when write cycle time or read cycle time
CSPULSEWIDTH (with I = 0 or 1) completes
Figure 7-14. Command Data Write
1578 Display Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated