Public Version
IPC Integration
www.ti.com
14.2.1.4 Power Management
14.2.1.4.1 System Power Management
This section describes system power management for the mailbox module.
As part of the system-wide power-management scheme, the mailbox module supports a communication
protocol with the PRCM that allows the PRCM to request the mailbox to enter a low-power state. When
the mailbox module acknowledges a low-power-mode request from the PRCM, the clock to the module is
gated off at the PRCM clock generator. Because the clock is disabled at the source, the low-power mode
offers lower power consumption than the internal clock-gating method in the local power management.
The PRCM.CM_ICLKEN1_CORE[7] EN_MAILBOXES bit in the PRCM module controls the mailbox clock.
When this bit is 1, the clock to the mailbox module is enabled; otherwise, the clock is disabled (see
, Power, Reset, and Clock Management, for more information).
The mailbox module can be configured using the MAILBOX.
[4:3] SIDLEMODE
field to one of the following acknowledgment modes:
•
No-idle mode: The mailbox module never enters the idle state.
•
Force-idle mode: The mailbox module immediately enters the idle state on receiving a low-power-mode
request from the PRCM module. In this mode, the software must ensure that there are no asserted
output interrupts before requesting this mode to go into the idle state.
•
Smart-idle mode: After receiving a low-power-mode request from the PRCM module, the mailbox
module enters the idle state only after all asserted output interrupts are acknowledged.
describes the mailbox power-management modes.
Table 14-1. Mailbox Power Management Modes
Power-Management Mode
[4:3] SIDLEMODE Bit Field
Requested by the PRCM
(Offset: 0x010)
Force-idle
00
No-idle
01
Smart-idle
10
Reserved (not used)
11
NOTE:
The mailbox idle status can be read from the PRCM.CM_IDLEST1_CORE[7]
ST_MAILBOXES bit. When this bit is 0, the mailbox module cannot be accessed; otherwise,
the mailbox module can be accessed (see
, Power, Reset, and Clock
Management, for more information).
14.2.1.4.2 Module Power Management
This section describes local power management for the mailbox module.
To conserve power, the mailbox module supports an automatic idle mode whenever no activity is detected
on the mailbox L4-Core interconnect interface. The automatic idle mode is enabled or disabled through
the MAILBOX.
[0] AUTOIDLE bit.
When the MAILBOX.
[0] AUTOIDLE bit is asserted, the automatic idle mode is
enabled in cases in which no activity is detected on the L4-Core interconnect interface, and the mailbox
clock is disabled internally to the module, thus reducing power consumption.
When new activity is detected on the L4-Core interconnect interface, the clock is restarted with no latency
penalty. After reset, the automatic idle mode is disabled; therefore, it is recommended that software
enable the automatic idle mode for reduced power consumption.
2648
Interprocessor Communication
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...