Texas Instruments OMAP36 Series, Техническое справочное руководство

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Functional Restrictions
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B.4.3 GPMC
The following general-purpose memory controller (GPMC) signals are not accessible outside the devices
in the CUS package:
• The gpmc_ncs1 and gpmc_ncs2 chip-select (CS) signals are not available at the device boundary
among the eight CSs supported by the GPMC.
• The gpmc_wait1 and gpmc_wait2 wait signals are not available at the device boundary among the four
wait signals supported by the GPMC.
• Address line gpmc_a11 is not available. As a result, the GPMC can support up to 128-MB memories,
in contrast to the CBP/CBC packages, where up to 256-MB POP memories can be supported.
NOTE: Cells highlighted in orange in Table B-2 indicate GPMC pins that have no dedicated balls on
the CUS package.
Table B-2 lists the GPMC subsystem I/O pins.
Table B-2. GPMC I/O Description
Pin Name I/O
(1)
Description
gpmc_a11 O Address
gpmc_a[10:1] O Address
gpmc_d[15:0] I/O Data/multiplexed address
gpmc_ncs0 O Chip-select (active low)
gpmc_ncs1 O Chip-select (active low)
gpmc_ncs2 O Chip-select (active low)
gpmc_ncs3 O Chip-select (active low)
gpmc_ncs4 O Chip-select (active low)
gpmc_ncs5 O Chip-select (active low)
gpmc_ncs6 O Chip-select (active low)
gpmc_ncs7 O Chip-select (active low)
gpmc_clk I/O Clock
(2)
gpmc_nadv_ale O Address valid (active low). Also used as address latch enable (active high)
for NAND protocol memories.
gpmc_noe_nre O Output-enable (active low). Also used as read-enable (active low) for NAND
protocol memories.
gpmc_nwe O Write-enable (active low)
gpmc_nbe0_cle O Lower-byte enable (active low). Also used as command latch enable for
NAND protocol memories.
gpmc_nbe1 O Byte 1 enable (active low)
gpmc_nwp O Write protect (active low)
gpmc_wait0 I External wait signal for NOR and NAND protocol memories
gpmc_wait1 I External wait signal for NOR and NAND protocol memories
gpmc_wait2 I External wait signal for NOR and NAND protocol memories
gpmc_wait3 I External wait signal for NOR and NAND protocol memories
gpmc_io_dir O gpmc_d[15:0] signal direction control:
• Low during transmit (for write access: data out from the GPMC to
memory)
• High during receive (for read access: data In from memory to the
GPMC)
(1)
I = Input, O = Output
(2)
This output signal is also used as retiming input.
3706OMAP36xx Multimedia Device in CUS Package SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated