iva2-003
PRCM
CORE_RST
RET_RST
IVA2_RSTPWRON
IVA2_RST1
IVA2_RST3
IVA2_RST2
IVA2_RST2
IVA2_RST3
IVA2_RST1
IVA2_PWR_RST
IVA2_RET_RST
IVA2_WGN_RST
IVA2.2 subsystem
CORE_RST domain
WUGEN
IVA2_RST3 domain
SEQ
IVA2_RST2 domain
iME
iVLCD
iLF
VIDEO
SYSC
SYSC
IVA2.2
MMU
EDMA
Local
interconnect
Local
memories
DSP
megamodule
IVA2_RST1 domain
Public Version
IVA2.2 Subsystem Integration
www.ti.com
across a warm reset sequence
•
IVA2_RSTPWRON, which performs a power-on initialization of IVA2.2 logic
Figure 5-3. IVA2.2 Subsystem Resets
After chip power on, the IVA2.2 subsystem is kept under reset and only the RET_RST is released from
reset. Then, only the WUGEN is released from reset as part of the core domain. The IVA2.2 remains
under reset until the microprocessor unit (MPU) clears the PRCM.RM_RSTCTRL_IVA2[1] RST2_IVA2 bit.
On this action, the PRCM switches on the IVA2.2 power domain, sets the clocks back, and releases the
power-on reset. When the IVA2.2 power-on sequence completes (hardware handshake), the PRCM
releases the IVA2_RST2 reset. At this stage, the DSP megamodule is kept under reset (unless the MPU
also cleared the PRCM.RM_RSTCTRL_IVA2[0] RST1_IVA2 bit); the MPU can upload some code and
data in the C64x+ memory. When the MPU has uploaded the code in the C64x+ memory, the MPU clears
the RST1_IVA2 bit, releasing the DSP megamodule from reset. At this point, the sequencer is kept under
reset (unless the PRCM.RM_RSTCTRL_IVA2[2] RST3_IVA2 bit was cleared); the DSP can upload some
code and data in the sequencer memory. When the DSP has uploaded the coded in the sequencer
memory, the DSP clears the RST3_IVA2 bit, releasing the sequencer from reset.
The MPU can apply a software reset to the IVA2.2. For a software reset to be safe, the IVA2.2 must be in
clock-off mode (DSP in idle mode with clocks shut down by the PRCM; for information about the clock-off
state transition, see
, Power-Down and Wake-Up Management.) For instance, the MPU
can use a mailbox interrupt to ask the IVA2.2 to go to IDLE state. In that case, only IVA2_RST1 and/or
IVA2_RST2 and/or IVA2_RST3 are applied, depending on which bits are set, and CORE_RST and
IVA2_RSTPWRON are never applied.
698
IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...