Public Version
Display Subsystem Register Manual
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Bits
Field Name
Description
Type
Reset
6
ECC_NO_CORRECTION_IRQ
ECC error status (short and long packets). No correction
RW
0x0
of the header because of more than 1-bit error.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
5
BTA_IRQ
Virtual channel - BTA status.
RW
0x0
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
4
FIFO_RX_OVF_IRQ
FIFO overflow error status. The FIFO used on the slave
RW
0x0
port for buffering the data received on the DSI link for the
VC has overflowed.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
3
FIFO_TX_OVF_IRQ
FIFO overflow error status. The FIFO used on the slave
RW
0x0
port for buffering the data received on the OCP slave port
for the VC has overflowed.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
2
PACKET_SENT_IRQ
Indicates that a packet has been sent. It is used when
RW
0x0
BTA manual mode is used.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
1
ECC_CORRECTION_IRQ
Virtual channel - ECC has been used to do the correction
RW
0x0
of the only 1-bit error status (short and long packet only).
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
0
CS_IRQ
Virtual channel - Check-Sum mismatch status.
RW
0x0
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
Table 7-431. Register Call Summary for Register DSI_VCn_IRQSTATUS
Display Subsystem Integration
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:
Display Subsystem Functional Description
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:
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Display Subsystem Basic Programming Model
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:
•
:
•
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Command Mode Transfer Example 1
:
•
Command Mode Transfer Example 2
:
Display Subsystem Register Manual
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DSI Protocol Engine Register Mapping Summary
1950Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
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Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
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Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
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