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Display Subsystem Basic Programming Model
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system memory to the DSI TX FIFO. Two independent DMA requests for RX FIFO and TX FIFO for the
same VC are supported. The read and write accesses can use burst structure. The DSI protocol engine
should access each write request in a burst without any IDLE between. For read OCP request in a burst to
RX FIFO, the acceptance is sent immediately and the response is delayed by at least four L4 interface
clock (DSS_L4_ICLK) cycles. In case of register reads, the response is returned in the first clock cycle.
The thresholds used for requests for the TX FIFO and RX FIFO are programmable by software. Users
program the DSS.
DSI_VCn_CTRL [19:17] DMA_TX_THRESHOLD and DSS. DSI_VCn_CTRL [26:24]
DMA_RX_THRESHOLD bit fields for TX FIFO and RX FIFO, respectively. Hardware asserts the DMA
request based on the threshold value. The size of the space allocated in TX FIFO for each VC must be a
multiple of the DSS.
DSI_VCn_CTRL [19:17] DMA_TX_THRESHOLD bit field value.
The only exception is in the case of the RX FIFO when the LP data transfer finishes and the threshold
value is not reached. In that case the DMA request must be asserted. Therefore, the drain of the FIFO is
supported in that configuration to empty the FIFO even if the number of data received is not a multiple of
the threshold value.
In case of TX FIFO, if all the bytes defined by the word count field in the
DSS.
DSI_VCn_LONG_PACKET_HEADER header register have been received, the DMA request is no
longer asserted even during the last transfer less than DMA_TX_THRESHOLD number of bytes have
been received because of the word count being not a multiple of the DMA_TX_THRESHOLD value.
In case of RX FIFO, while the DMA request is used to transfer the data from the RX FIFO to the system
memory, the system DMA must be programmed to read the number of received bytes in the FIFO. If users
do not know the size of the received bytes, the direct access of the RX FIFO through the
DSS.
DSI_VCn_SHORT_PACKET_HEADER register is performed until the DSS. DSI_VCn_CTRL [20]
RX_FIFO_NOT_EMPTY bit goes to 0.
The use of each DMA request is programmable by software. The DSS. DSI_VCn_CTRL [23:21]
DMA_TX_REQ_NB is dedicated to DMA request numbering for the TX FIFO. The
DSS.
DSI_VCn_CTRL [29:27] DMA_RX_REQ_NB is dedicated to DMA request numbering for the RX
FIFO.
When the DMA request is used to indicate the number of 32-bit values ready in the RX FIFO or BTA has
been received from peripheral indicating end of the transfer from peripheral to host for a transfer to the
system memory, the DMA request corresponding to the VC ID is generated.
The system DMA transfers the number of 32-bit values defined in the threshold register or the exact
number of bytes received from the peripheral (user should know the number of expected received bytes to
program correctly the system DMA). When the system DMA transfers a multiple number of threshold
value, the DSI protocol engine should send 0s for the data when there is no more received data in the RX
FIFO for the VC. Software users must parse the data and determine the valid bytes.
Software users can decide to determine the number of data received in the RX FIFO to read the
information in the DSS.
DSI_RX_FIFO_VC_FULLNESS register. Then the system DMA can be
programmed to read the number of bytes from the RX FIFO. The BTA interrupt (BTA_IRQ) must be used
to know when to read the number of received bytes. To monitor the BTA interrupt, the user must read the
DSS.
DSI_VCn_IRQSTATUS [5] BTA_IRQ status bit. The DMA request must not be selected until the
system DMA is programmed with the correct number of data to read from RX FIFO.
If the RX FIFO space for the VC is expected to be overflow because the number of data to be received is
greater than the space allocated for the VC, the previous programming model must be used. In place, the
DMA request must be asserted as soon as the threshold is reached or when BTA is received.
When the DMA request is used to indicate the number of 33-bit entries empty in the TX FIFO for a
transfer from the system memory, the DMA request corresponding to the VC ID is generated.
NOTE: To obtain best efficiency of the transfer the size of the request (read or write, single or burst)
must be aligned with the threshold value.
Concurrent access using interlaced requests (read/write) to the TX and RX FIFO is supported for the
same VC ID or different VC IDs.
1746 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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