Texas Instruments OMAP36 Series, Техническое справочное руководство

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McBSP Functional Description
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Table 21-19. Effects of DLB and ALB Bits on Clock Modes (continued)
Mode Bit Settings Effect
CLKXM= 1 DLB=0 & ALB = 0 (Digital & analog loop back mode mcbspi_clkx is an output pin driven by the SRG output clock
disabled) (CLKG).
DLB=0 & ALB = 1 (Digital loop back mode disabled and mcbspi_clkx is an output pin driven by the SRG output clock
Analog loop back mode enabled) (CLKG).
DLB=1 & ALB = 0 (Digital loop back mode enabled and The SRG and the frame synchronization generator need to be
Analog loop back mode disabled) enabled.
The internal transmit and receive clocks are driven by the SRG
(CLKG having the appropriate CLKXP polarity).
The transmit and receive frame synchronization signals are driven
by FSG (having the appropriate FSXP polarity).
The transmit data is connected to the DR input data.
Note that in digital loop back mode no serial link activity will be
seen by the remote device.
DLB=1 & ALB = 1 (reserved mode) Undefined functionality.
SCM.CONTROL_DEVCONF0[3] MCBSP1_CLKR bit =1 CLKX is an output pin driven by the SRG output clock (CLKG).
(synchronous setting and DLB = 0 & ALB = 0) CLKR is connected to the CLKX.
21.4.3.2 Frame Sync Generation in the SRG
The SRG can produce a frame-synchronization signal (FSG) for use by the receiver, the transmitter, or
both.
If you want the receiver to use FSG for frame synchronization, make sure
McBSPi.
MCBSPLP_PCR_REG [10] FSRM bit =1. (When FSRM=0, receive frame synchronization is
supplied via the mcbspi_fsr pin.)
If you want the transmitter to use FSG for frame synchronization, you must set:
• McBSPi. MCBSPLP_PCR_REG [11] FSXM = 1: This indicates that transmit frame synchronization is
supplied by the McBSP module itself rather than from the mcbspi_fsx pin.
• MCBSPLP_SRGR2_REG [12] FSGM=1: This indicates that when FSXM=1, transmit frame
synchronization is supplied by the SRG.
NOTE: When FSGM=0 and FSXM=1, the transmit frame-sync signal (FSX) is generated when XB
is not empty. When FSGM = 0, McBSPi. MCBSPLP_SRGR2_REG [11:0] FPER and
McBSPi. MCBSPLP_SRGR1_REG [15:8] FWID field are used to determine the frame
synchronization period and width (external FSX is gated by the buffer empty condition).
In either case, the SRG must be enabled (McBSPi. MCBSPLP_SPCR2_REG [6] GRST bit=1) and the
frame-synchronization logic in the SRG must be enabled (McBSPi. MCBSPLP_SPCR2_REG [7] FRST
bit=0).
21.4.3.2.1 Choosing the Width of the Frame-sync Pulse
Each pulse on FSG has a programmable width. You program the McBSPi. MCBSPLP_SRGR1_REG [15:8]
FWID field, and the resulting pulse width is (FWID+1)CLKG cycles, where CLKG is the output clock of the
SRG. The range is from 1 to 256 clock periods.
21.4.3.2.2 Controlling the Period Between the Starting Edges of Frame Sync Pulses
You can control the amount of time from the starting edge of one FSG pulse to the starting edge of the
next FSG pulse. This period is controlled in one of two ways, depending on the configuration of the SRG:
• If the SRG is using an external input clock and McBSPi. MCBSPLP_SRGR2_REG [15] GSYNC bit =1,
FSG pulses in response to an inactive-to-active transition on the mcbspi_fsr pin. Thus, an external
device controls the frame-synchronization period.
3106 Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
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