Texas Instruments OMAP36 Series, Техническое справочное руководство

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General-Purpose Memory Controller
to the WAITxEDGEDETECTIONSTATUS bit (x = 0 to 3) of the GPMC. GPMC_IRQSTATUS register
according to the gpmc_wait pin used for the NAND device-ready signal monitoring. To detect a
wait-to-no-wait transition, the transition detector requires a wait active time detection of a minimum of two
GPMC_FCLK cycles. Software must incorporate precautions to clear the wait transition pin detector before
wait (busy) time completes.
A wait-to-no-wait transition detection can issue a GPMC interrupt if the WAITxEDGEDETECTIONENABLE
bit in the GPMC.
GPMC_IRQENABLE register is set and if the WAITxEDGEDETECTIONSTATUS bit field
in the GPMC. GPMC_IRQSTATUS register is set.
The WAITMONITORINGTIME field does not affect wait-to-no-wait transition time detection.
It is also possible to poll the WAITxEDGEDETECTIONSTATUS bit field in the GPMC. GPMC_IRQSTATUS
register according to the gpmc_wait pin used for the NAND device ready signal monitoring.
10.1.5.14.3 ECC Calculator
The general-purpose memory controller includes an error code correction (ECC) calculator circuitry that
enables on-the-fly ECC calculation during data read or data program (that is, write) operations.
The user can choose from two different algorithms with different error correction capabilities: Hamming
code (for 1-bit error code correction), and BCH code (for 4- or 8-bit error correction) through the
GPMC_ECC_CONFIG [16] ECCALGORITHM bit. Only one ECC context can be active at any given time
through the GPMC_ECC_CONFIG [3:1] ECCCS bit. Even if two CSs use different ECC algorithms, one the
Hamming code and the other a BCH code, they must define separate ECC contexts, because some of the
ECC registers are common to all types of algorithms.
10.1.5.14.3.1 Hamming Code
All references to ECC in this section refer to the 1-bit error correction Hamming code.
The ECC is based on a two-dimensional (row and column) bit parity accumulation known as Hamming
code. The parity accumulation is done for a programmed number of bytes or Word16 read from the
memory device or written to the memory device in stream mode.
There is no automatic error detection or correction, and it is the software NAND driver responsibility to
read the multiple ECC calculation results, compare them to the expected code value, and take the
appropriate corrective actions according to the error handling strategy (ECC storage in spare byte, error
correction on read, block invalidation).
The ECC engine includes a single accumulation context. It can be allocated to a single designated
chip-select at a time and parallel computations on different chip-selects are not possible. Since it is
allocated to a single chip-select, the ECC computation is not affected by interleaved GPMC accesses to
other chip-selects and devices. The ECC accumulation is sequentially processed in the order of data read
from or written to the memory on the designated chip-select. The ECC engine does not differentiate read
accesses from write accesses and does not differentiate data from command or status information. It is
the software responsibility to make sure only relevant data are passed to the NAND flash memory while
the ECC computation engine is active.
The starting NAND page location must be programmed first, followed by an ECC accumulation context
reset with an ECC enabling, if required. The NAND device accesses discussed in the following sections
must be limited to data read or write until the specified number of ECC calculations is completed.
10.1.5.14.3.1.1 ECC Result Register and ECC Computation Accumulation Size
The GPMC includes up to nine ECC result registers (GPMC. GPMC_ECCj_RESULT , j = 1 to 9) to store
ECC computation results when the specified number of bytes or Word16s has been computed.
The ECC result registers are used sequentially; one ECC result is stored in one ECC result register on the
list, the next ECC result is stored in the next ECC result register on the list, and so forth, until the last ECC
computation. The GPMC.
GPMC_ECCj_RESULT register value is valid only when the programmed
number of bytes or Word16s has been accumulated, which means that the same number of bytes or
Word16s has been read from or written to the NAND device in sequence.
2163 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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