Texas Instruments OMAP36 Series, Техническое справочное руководство

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General-Purpose Memory Controller
Table 10-76. Register Call Summary for Register GPMC_PREFETCH_STATUS
General-Purpose Memory Controller
• NAND Device Basic Programming Model : [0] [1] [2] [3] [4] [5] [6]
• GPMC Register Summary : [7]
Table 10-77. GPMC_ECC_CONFIG
Address Offset 0x0000 01F4
Physical Address 0x6E00 01F4 Instance GPMC
Description ECC configuration
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ECCCS
ECC16B
ECCBCHT8
RESERVED
ECCENABLE
ECCALGORITHM ECCWRAPMODE
ECCTOPSECTOR
Bits Field Name Description Type Reset
31:17 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0000
16 ECCALGORITHM ECC algorithm used RW 0x0
0x0: Hamming code
0x1: BCH code
15:13 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0
12 ECCBCHT8 Error correction capability used for BCH RW 0x1
0x0: Up to 4 bits error correction (t = 4)
0x1: Up to 8 bits error correction (t = 8)
11:8 ECCWRAPMODE Spare area organization definition for the BCH algorithm. See the RW 0x0
BCH syndrome/parity calculator module functional specification
for more details
7 ECC16B Selects an ECC calculated on 16 columns RW 0x0
0x0: ECC calculated on 8 columns
0x1: ECC calculated on 16 columns
6:4 ECCTOPSECTOR Number of sectors to process with the BCH algorithm RW 0x3
0x0: 1 sector (512kB page) 0x1: 2 sectors
...
0x3: 4 sectors (2kB page)
...
0x7: 8 sectors (4kB page)
3:1 ECCCS Selects the CS where ECC is computed RW 0x0
0x0: Chip-select 0
0x1: Chip-select 1
0x2: Chip-select 2
0x3: Chip-select 3
0x4: Chip-select 4
0x5: Chip-select 5
0x6: Chip-select 6
0x7: Chip-select 7
0 ECCENABLE Enables the ECC feature RW 0x0
0x0: ECC disabled
0x1: ECC enabled
2217 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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