Texas Instruments OMAP36 Series, Техническое справочное руководство

Страница: 1014 / 3738

Public Version
IVA2.2 Subsystem Register Manual
www.ti.com
Table 5-551. Register Call Summary for Register VLCD_VLCDIN_ADDR
IVA2.2 Subsystem Basic Programming Model
• Setting Up Registers for VLC Operation : [0]
• Setting Up Registers for VLD Operation : [1]
• Calculating the Number of Bits Processed During a VLD Run : [2] [3]
IVA2.2 Subsystem Register Manual
• iVLCD Register Mapping Summary : [4]
Table 5-552. VLCD_VLCDOUT_ADDR
Address Offset 0x0000 101C
Physical Address 0x0008 101C Instance iVLCD
Description This register sets the output address for the variable length coder and decoder operations.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADDR
RESERVED
MEMSELECT
Bits Field Name Description Type Reset
31:16 RESERVED Write 0s for future compatibility RW 0x0000
Read returns 0
15 MEMSELECT Sets the buffer used for the computation RW 0x0
0: IMG BUF A/B
1: IMG BUF1
14:13 RESERVED Write 0s for future compatibility RW 0x0
Read returns 0
12:0 ADDR Sets the start address for the computation RW 0x0000
Table 5-553. Register Call Summary for Register VLCD_VLCDOUT_ADDR
IVA2.2 Subsystem Basic Programming Model
• Setting Up Registers for VLC Operation : [0]
• Setting Up Registers for VLD Operation : [1]
IVA2.2 Subsystem Register Manual
• iVLCD Register Mapping Summary : [2]
Table 5-554. VLCD_DC_PREDj
Address Offset 0x0000 1020 + (0x4*j)
Physical Address 0x0008 1020 + (0x4*j) Instance iVLCD
Description This register sets the initial/final DC predictors for Quantization
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PRED
Bits Field Name Description Type Reset
31:12 RESERVED Write 0s for future compatibility RW 0x0
Read returns 0
11:0 PRED Initial/ final DC predictor value RW 0x000
1014 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated