Public Version
PRCM Functional Description
www.ti.com
For example, if L0 is the lower voltage and an active-low polarity (default setting) on the sys_nvmode[1,2]
signal:
•
L0 logical level sys_nvmode[1,2] = 1 VDD = OPP100
•
L1 logical level sys_nvmode[1,2] = 0 VDD = LOW
The polarity of the logical voltage-level signal from the PRM can be controlled by the
PRCM.
[0] EXTVOL_POL bit. It is active-low by default (L0 = 1, L1 = 0).
3.5.6.5.2 Direct Voltage Control With I
2
C Interface
PRM can send VDD1 and VDD2 sleep commands to the power IC through the dedicated I
2
C. This allows
the power IC to activate sleep mode (the voltage regulator switches in sleep mode, where voltage is
maintained but only small load is supported). This also allows external power IC to reduce its power
consumption.
3.5.6.5.3 Voltage Controller and Dedicated SmartReflex I
2
C Interface
The dedicated I
2
C voltage control mode is dedicated to SmartReflex technology. The central modules for
the I
2
C control mode are the voltage controller and the I
2
C interface. The voltage controller receives
voltage control commands from five input ports:
•
Voltage processor 1 and 2 ports: The voltage processors send commands to the voltage controller
depending on the SmartReflex module calculations (during device activity).
•
Voltage FSM 1 and 2 ports: The voltage FSMs send commands to the voltage controller when the
device enters retention or off power state, and also when the device wakes up.
•
PRM register port: The PRM registers give direct software control over the voltage levels of the VDD1
and VDD2 voltage domains.
An arbitration scheme in the voltage controller manages concurrent requests on multiple ports.
Externally, the voltage controller interfaces to a power IC through a dedicated I
2
C interface (I2C4). To
reduce the latency of voltage changes, the voltage controller is configurable to run in HS I
2
C mode.
Each internal port has a handshake to indicate when the I
2
C frame that results from the request on that
port is acknowledged by the external power IC.
3.5.6.5.4 SmartReflex Voltage Control
As explained previously (see
, SmartReflex Adaptive Voltage Scaling), SmartReflex
technology uses adaptive power control to reduce active power consumption by the device. SmartReflex
voltage control in the device is based on the dedicated SmartReflex modules and the voltage processors,
in addition to the voltage controller and I
2
C interface, which are shared with the voltage FSMs and voltage
control registers.
The SmartReflex modules allow a continuous real-time voltage supply and device performance monitoring
to do the following:
•
Minimize the supply voltage to reduce the device power consumption.
•
Maintain the desired device performance (by dynamically adjusting the device voltage) as the
temperature of the device varies.
Within the device, the SmartReflex modules can be used to stabilize performance at a given OPP or for
the DVFS (that is, switching from one OPP to another).
Because the SmartReflex modules and the voltage processors are dedicated to SmartReflex voltage
control, they are described together in this section.
3.5.6.5.4.1 SmartReflex in the Device
shows the SmartReflex integration.
380
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...