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SDRAM Controller (SDRC) Subsystem
Table 10-176. Register Call Summary for Register SDRC_MR_p
SDRAM Controller (SDRC) Subsystem
• SDRC Power-Down Mode : [0]
• Mode Register (MR) : [1] [2] [3] [4] [5] [6]
• Mode Register Programming and Modes of Operation : [7] [8] [9]
• Low-Power SDR/Mobile DDR Initialization Sequence : [10]
• Read/Write Access : [11]
• SDRC Register Summary : [12]
• SDRC Register Description : [13] [14]
Table 10-177. SDRC_EMR2_p
Address Offset 0x0000 008C + (0x0000 0030 * p) Index p = 0 to 1
Physical Address 0x6D00 008C + (0x0000 0030 * p) Instance SDRC
Description This 12-bit register corresponds to the low-power EMR register, as defined in the mobile DDR JEDEC Standard.
All 12 bits are loaded into the memory, thus assuring future extension support. The SDRC keeps an internal
copy register used internally; that is, returned when a read access is performed at that address. Load into
memory on interconnect write access using MRS command with BA1,BA0 = 1,0.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ZERO DS TCSR PASR
Bits Field Name Description Type Reset
31:12 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00000
11:7 ZERO Write 0s, as required by memory specifications. Read returns 0 RW 0x00
6:5 DS Driver strength RW 0x0
0x0: Full strength driver
0x1: Weak strength driver
0x2: Reserved
0x3: Reserved
4:3 TCSR Temperature-compensated self-refresh RW 0x0
0x0: 70 degrees maximum temperature
0x1: 45 degrees maximum temperature
0x2: 15 degrees maximum temperature
0x3: 85 degrees maximum temperature
2:0 PASR Partial array self-refresh RW 0x0
0x0: All banks.
0x1: 1/2 array
0x2: 1/4 array
0x3: Reserved
0x4: Reserved
0x5: 1/8 array
0x6: 1/16 array
0x7: Reserved
2327 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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