Texas Instruments OMAP36 Series, Техническое справочное руководство

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SDRAM Controller (SDRC) Subsystem
All settings for the power-saving features are common to the two CSs. When two CSs are used, however,
only the accessed CS exits self-refresh or deep-power-down mode.
If the SDRC. SDRC_POWER_REG [6] SRFRONIDLEREQ bit is enabled, the SDRC enters self-refresh
mode on a hardware idle request from the PRCM. The memory clock is automatically switched off, after
which the SDRC sends an acknowledge back to the PRCM. In this situation, the power manager can
switch the SDRC clock off. Therefore, if the SDRC is connected to a DDR memory, and if the DLL is
enabled and in TrackingDelay mode, the SDRC waits for the lock status bit of the DLL to be asserted
before accessing the memory when the system exits the idle state. The WAKEUPPROC bit of the
SDRC_POWER_REG register enables the SDRC to automatically wait for 500 cycles (DLL relocking
maximum time) before accessing the memory instead of using the LOCK signal. These 500 wait cycles
are obeyed only when the DLL is set in TrackingDelay mode. For SDR mode and DLL ModeFixedDelay
mode, the access is processed immediately. This mechanism is independent of the CLKCTRL field.
NOTE: DLL Behavior Upon a Warm Reset Assertion:
Upon a warm reset (the SDRC_DLLA_CTRL [3] ENADLL bit is not reset as it is not sensitive
to warm reset but the DLL will be in unlock mode since DLL is reset. To lock the DLL again,
the
SDRC_DLLA_CTRL [3] ENADLL needs to be made 0 and then made 1 again. This will
trigger a locking sequence.
10.2.4.4.9.3 Static Low-Power Operating Modes
The software-driven controls for low-power operation modes include:
• Possibility to put the memory in self-refresh using the manual command register
(SDRC.
SDRC_MANUAL_p (where p = 0 or 1 for SDRC CS0 or CS1). Each CS can be controlled
independently. If both CSs are in self-refresh, the external SDRAM clock can be switched off by setting
the SDRC.
SDRC_POWER_REG [3] EXTCLKDIS control bit to 1. Self-refresh can be exited
automatically if an access is initiated onto the CS. Only DPD must be exited manually.
• Possibility to put the memory in deep-power-down mode, if supported by the SDRAM, using the
manual command register. Each CS can be controlled independently. The external SDRAM clock can
be switched off if both CSs are either in self-refresh or deep-power-down mode by setting the
SDRC.
SDRC_POWER_REG [3] EXTCLKDIS control bit to 1. Another manual command must be used
for the memory to exit deep-power-down mode. After a memory exits from that mode all data are lost,
and a full initialization sequence must be sent to the device, before it can be used.
10.2.4.4.10 SDRC Power-Down Mode
In some applications, the SDRC power domain can be powered down while the external memory is in
self-refresh mode.
When the SDRC is powered off, an isolation stage prevents an unwanted exit from self-refresh when the
context is restored. SDRC outputs that control the SDRAM are set to maintain self-refresh or
deep-power-down (CKE low).
When a reset occurs, the default reset state of the SDRC is power-down enable (PDE).
When exiting the off mode:
• Power is restored to the SDRC.
• The software reconfigures all registers. If the NOMEMORYMRS bit is set, the MR and EMR registers
can be set through the SDRC.
SDRC_MR_p and SDRC. SDRC_EMR2_p registers (see
Section 10.2.4.5 , Mode Registers).
• Exit from self-refresh mode is achieved through the SDRC. SDRC_MANUAL_p CMDCODE field.
Because exit from the self-refresh field is unconditional (that is, the current state of the SDRC
state-machine is not considered), ensure that autorefresh is disabled.
Once the context is successfully restored, the software can reinitialize the SDRAM or return the SDRAM
to self-refresh. When the device successfully exits self-refresh, autorefresh must be re-enabled.
2259 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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