Texas Instruments OMAP36 Series, Техническое справочное руководство

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General-Purpose Memory Controller
Bits Field Name Description Type Reset
1 P2e Even column parity bit 2 R 0x0
0 P1e Even column parity bit 1 R 0x0
Table 10-84. Register Call Summary for Register GPMC_ECCj_RESULT
General-Purpose Memory Controller
• NAND Device Basic Programming Model : [0] [1] [2] [3] [4] [5] [6] [7]
• GPMC Register Summary : [8]
Table 10-85. GPMC_BCH_RESULT0_i
Address Offset 0x0000 0240 + (0x0000 0010 * i) Index i = 0 to 7
Physical Address 0x6E00 0240 + (0x0000 0010 * i) Instance GPMC
Description BCH ECC result (bits 0 to 31)
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT_0
Bits Field Name Description Type Reset
31:0 BCH_RESULT_0 BCH ECC result (bits 0 to 31) RW 0x00000000
Table 10-86. Register Call Summary for Register GPMC_BCH_RESULT0_i
General-Purpose Memory Controller
• NAND Device Basic Programming Model : [0]
• GPMC Register Summary : [1]
Table 10-87. GPMC_BCH_RESULT1_i
Address Offset 0x0000 0244 + (0x0000 0010 * i) Index i = 0 to 7
Physical Address 0x6E00 0244 + (0x0000 0010 * i) Instance GPMC
Description BCH ECC result (bits 32 to 63)
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCH_RESULT_1
Bits Field Name Description Type Reset
31:0 BCH_RESULT_1 BCH ECC result (bits 32 to 63) RW 0x00000000
Table 10-88. Register Call Summary for Register GPMC_BCH_RESULT1_i
General-Purpose Memory Controller
• NAND Device Basic Programming Model : [0]
• GPMC Register Summary : [1]
2221 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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