Texas Instruments OMAP36 Series, Техническое справочное руководство

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IVA2.2 Subsystem Register Manual
Table 5-90. XMC Register Summary (continued)
Register Name Type Register Width Address Offset Physical Address
(Bits)
L2MPPAj
(2)
RW 32 0x0000 A200 + (0x4*j) 0x0184 A200 + (0x4*j)
L1PMPFAR R 32 0x0000 A400 0x0184 A400
L1PMPFSR R 32 0x0000 A404 0x0184 A404
L1PMPFCR W 32 0x0000 A408 0x0184 A408
L1PMPPAk
(3)
RW 32 0x0000 A600 + (0x4*k) 0x0184 A600 + (0x4*k)
L1DMPFAR R 32 0x0000 AC00 0x0184 AC00
L1DMPFSR R 32 0x0000 AC04 0x0184 AC04
L1DMPFCR W 32 0x0000 AC08 0x0184 AC08
L1DMPPAk
(3)
RW 32 0x0000 AE00 + (0x4*k) 0x0184 AE00 + (0x4*k)
(2)
j = 0 to 64
(3)
k = 0 to 32
5.5.4.2 XMC Register Descriptions
Table 5-91. L2CFG
Address Offset 0x0000 0000
Physical address 0x0184 0000 Instance IVA2.2 GEMXMC
Description L2 cache configuration register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved NUM_MM Reserved MMID Reserved IP ID Reserved L2CC L2MODE
NOINIT
Bits Field Name Description Type Reset
31:28 Reserved Write 0s for future compatibility. Read returns 0. R 0x0
27:24 NUM_MM Number of megamodules -1 (always 0 for IVA2) R 0x0
23:20 Reserved Write 0s for future compatibility. Read returns 0. R 0x0
19:16 MMID Megamodule ID (always 0x0 for IVA2) R 0x0
15:11 Reserved Write 0s for future compatibility. Read returns 0. W 0x00
10 NOINIT No init upon cache config: when written '1', cache config is restored W 0
without re-initializing cache context (tags, validity bits) (this is
assumed here that the restored cache settings are the same as prior
to the execution of the IDLE instruction) when written '0', cache
context is re-initialized (cache content is indirectly lost) this bit is
always read as 0
9 IP Global L1P invalidate (for backward compatibility,deprecated) W 0
8 ID Global L1D invalidate (for backward compatibility,deprecated) W 0
7:5 Reserved Write 0s for future compatibility. Read returns 0. W 0x0
4:3 L2CC L2 cache control RW 0x0
0x0: L2 cache operates normally
0x1: L2 Cache is frozen
0x2: L2 cache is bypassed
2:0 L2MODE L2 Configuration Register RW 0x0
0x0: 0KB of L2 Cache
0x1: 32KB of L2 Cache
0x2: 64KB of L2 Cache
829 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated