Texas Instruments OMAP36 Series, Техническое справочное руководство

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Display Subsystem Use Cases and Tips
Software users must remember to change the clock configuration after enabling DPLL4 when leaving
low-power mode by setting the DSS.
DSS_CONTROL [0] DISPC_CLK_SWITCH bit to 0x0. The
DSS1_ALWON_FCLK clock will be selected.
Lock time must be considered before disabling the DSS1_ALWON_FCLK clock.
7.6.2.4 Autoidle and Smart Idle
7.6.2.4.1 Autoidle
To further save power consumption, the autoidle feature at the module can be enabled for the active
modules. For example, the PRCM and the system control modules are active during this mode. By
enabling the autoidle feature, the clocks at the module level are gated when they are not needed.
The RFBI, display controller, and L4 interfaces can internally gate their clocks to decrease power
consumption if no transaction is present on the related bus. The following bits must be set to enable this
functionality:
•
DSS. DSS_SYSCONFIG [0] AUTOIDLE bit (1: Autoidle; 0: Clock free-running) for the display subsystem
• DSS. RFBI_SYSCONFIG [0] AUTOIDLE bit (1: Autoidle; 0: Clock free-running) for the RFBI
• DSS. DISPC_SYSCONFIG [0] AUTOIDLE bit (1: Autoidle; 0: Clock free-running) for the display
controller
• DSS. DISPC_CONFIG [9] FUNCGATED bit (1: Functional clocks gated enabled, 0: Functional clocks
gated disabled) for the display controller
7.6.2.4.2 Smart-Idle
The smart-idle feature can be enabled to allow the module to enter idle when the clocks are not needed.
The smart-idle feature can be enabled for the display subsystem submodules to further save power
consumption:
•
Display subsystem: DSS. DSS_SYSCONFIG [4:3] SIDLEMODE
• Display controller: DSS. DISPC_SYSCONFIG [4:3] SIDLEMODE
• RFBI: DSS. RFBI_SYSCONFIG [4:3] SIDLEMODE
7.6.2.5 FIFO Thresholds
The display subsystem internal FIFO is used to move data to the LCD panel. This FIFO is filled by the
display subsystem DMA controller. The DMA controller is triggered to start and stop based on two
thresholds:
•
DSS. DISPC_GFX_FIFO_THRESHOLD [11:0] GFXFIFOLOWTHRESHOLD
• DSS. DISPC_GFX_FIFO_THRESHOLD [27:16] GFXFIFOHIGHTHRESHOLD
When the level of the FIFO reaches the low threshold, the internal DMA controller begins to fill the FIFO
With the data in the frame buffer. Once the amount of pixel data reaches the high threshold, the internal
DMA controller stops.
7.6.2.5.1 FIFO Threshold Settings to Reduce Power Consumption
Power consumption is reduced by increasing the difference between the high and low FIFO threshold
levels, thereby leaving the SDRAM in self-refresh for a longer period of time. To perform this reduction,
consider the following:
•
The low FIFO threshold level must be as low as possible, but not low enough to cause any underflow.
• The high FIFO threshold level must not exceed the FIFO size minus one burst. A value above this limit
results in the DMA controller trying to fill the FIFO to a level that cannot be reached, which will increase
power consumption.
• The difference between high and low FIFO threshold levels must not be less than one burst size.
These settings do not reduce power consumption because the SDRAM never goes into self-refresh,
but they will avoid underflow.
1791 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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