Texas Instruments OMAP36 Series, Техническое справочное руководство

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Finp
Fref
Fout
1
N+1
Phase
detector
Digital
controlled
oscillator
1
M
1
M2
scm-033
Spreading
generation
block
Loop
filter
Public Version
SCM Functional Description
www.ti.com
13.4.11 EMI Reduction for Clocking Generation (Spreading)
13.4.11.1 Overview
There are two major forms of digital signals: digital-data and digital-clock (CLK). Digital signals are the
principal signal form in today's digital electronic products.
•
A digital-data signal can be viewed as a sequence of pulses with different pulse widths
• A clock (CLK) signal is usually a string of rectangular pulses with the same pulse width
In the case of a clock, the generated signal has a predetermined frequency. Electromagnetic radiations
such as radio frequency emissions are also generated from the constant frequency clock signals and their
harmonics. Unfortunately, a problem exists with some devices such as communication devices for
example in that the system clock generates unwanted spurious signals that interfere with the decoding of
information from received signals by a receiver of the communication device. Note that data periodicity
also causes interference.
This periodicity generates a significant power peak at the selected frequency, which in turn causes an EMI
disturbance to the environment.
The harmonics of the generated signal system clock radiates in the other modules of the device, and the
spurious energy can be enough to cause enough interference, which results in performance degradation
(in the form of high bit error rates in case of a wireless communication interface for example).
To reduce the power peaks (and thus the energy of the electromagnetic noise generated for a specific
frequency), an internal frequency modulation of the digital phase-locked loop (DPLL) is used to distribute
the energy to many different frequencies, thus reducing the power peaks.
This frequency modulation feature is directly integrated in some DPLLs of the device. The DPLLs that
support this additional feature are called DPLL-D in the following.
Figure 13-18 is a diagram of a DPLL that supports the EMI reduction feature.
Figure 13-18. DPLL With EMI Reduction Feature
The additional features of the DPLL compliant with EMI reduction are:
• EMI reduction using triangular frequency modulation, also called spread sprectrum clocking (SSC).
2522 System Control Module SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated