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sdrc-042
8192 rows 8192 rows 8192 rows 8192 rows
1024 columns 1024 columns 1024 columns 1024 columns
Bank 0 Bank 1 Bank 2 Bank 3
Column Decoder Column Decoder Column Decoder Column Decoder
RowDecoder RowDecoder RowDecoder RowDecoder
A0-A12 CK CS
Address Buffer
Row Address Latch
Refresh Counter Timing Generator
Bank Control
DQS0
DQS1
DQ0
DQ15
Column Address Latch
CKE WE RAS CAS
Public Version
SDRAM Controller (SDRC) Subsystem
www.ti.com
Figure 10-52. SDRAM Controller Block Diagram
10.2.4.4.4.2 SDRC Controller Commands
Before any read or write command can be issued to a bank in the external memory, a row in that bank
must be opened. This is accomplished by the active command, by which the bank and the row are
selected. More than one bank (up to four according to the memory used) can be active at one time. Once
a row is opened, a read or write command can be issued to that row. The row remains active until a
precharge or read/write to another row in the same bank or a refresh to the bank occurs.
Autorefresh command is used during normal operation mode. This command is non-persistent (that is, it
must be issued each time a refresh is required). The device requires a refresh of all rows in a periodic
interval. This command takes some time (according to the memory used), and during this phase no read
or write command can be processed. A precharge-all (that is, a precharge command affecting all banks) is
issued before any autorefresh sequence.
An active command to a row of a bank for which another row is already active can be issued only after the
previous row has been closed. The precharge command is used to deactivate the open row in a particular
bank. The bank is available for a subsequent row access some time after the row precharge command is
issued. A minimum time is needed to close and open a new row.
A subsequent active command to another bank can be issued while the first bank is being accessed
without closing the row in the first bank. This results in a reduction of row access time in the same bank.
In this case, it is not necessary to deactivate (with a precharge command) the row in the other banks. Up
to four banks, depending on the memory used, can be activated at the same time. In each bank, one row
can be selected at a time.
10.2.4.4.4.3 BANKALLOCATION Parameter
To optimize SDRAM memory accesses in a throughput point of view, the SDRC controller supports
various bank-row-column allocation. The bank-row-column allocation choice depends on many
parameters, such as the number of initiators in the use case, the memory usage (accesses bandwidth,
frequency), and so on.
The SDRC controller not only supports the regular allocation where the system address bus is seen as the
concatenation bank-row-column, but it also supports two other types of allocation. The
SDRC_MCFG_p [7:6] BANKALLOCATION bit field (where p = 0 or 1 for CS0 or CS1) selects the type of
allocation. This feature modifies the bank, row, and column address decoding order:
2250 Memory Subsystem SWPU177N – December 2009 – Revised November 2010
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