Texas Instruments OMAP36 Series, Техническое справочное руководство

Страница: 3432 / 3738

Public Version
MMC/SD/SDIO Register Manual
www.ti.com
Bits Field Name Description Type Reset
14 OBIE Out-of-Band Interrupt Enable (MMC cards only). RW 0
This bit enables the detection of Out-of-Band Interrupt on
MMCOBI input pin. The usage of the Out-of-Band signal (OBI) is
optional and depends on the system integration.
0x0: Out-of-Band interrupt detection disabled.
0x1: Out-of-Band interrupt detection enabled.
13 OBIP Out-of-Band Interrupt Polarity (MMC cards only). RW 0
This bit selects the active level of the out-of-band interrupt coming
from MMC cards. The usage of the Out-of-Band signal (OBI) is
optional and depends on the system integration.
0x0: active high level.
0x1: active low level.
12 CEATA CE-ATA control mode (MMC cards compliant with CE-ATA): RW 0
By default, this bit is set to 0. It is use to indicate that next
commands are considered as specific CE-ATA commands that
potentially use 'command completion' features.
0x0: Standard MMC/SD/SDIO mode.
0x1: CE-ATA mode.
Next commands are considered as CE-ATA
commands.
11 CTPL Control Power for mmci_dat[1] line (MMC and SD cards): RW 0
By default, this bit is set to 0 and the host controller automatically
disables all the input buffers outside of a transaction to minimize
the leakage current.
SDIO cards:
When this bit is set to 1, the host controller automatically disables
all the input buffers except the buffer of mmci_dat[1] outside of a
transaction in order to detect asynchronous card interrupt on
mmci_dat[1] line and minimize the leakage current of the buffers.
0x0: Disable all the input buffers outside of a transaction.
0x1: Disable all the input buffers except the buffer of
mmci_dat[1]
outside of a transaction.
10:9 DVAL Debounce filter value (All cards) RW 0x3
This register is used to define a debounce period to filter the card
detect input signal (SDCD). The usage of the card detect input
signal (SDCD) is optional and depends on the system integration
and the type of the connector housing that accommodates the
card.
0x0: 33 us debounce period.
0x1: 231 us debounce period.
0x2: 1 ms debounce period.
0x3: 8.4 ms debounce period.
8 WPP Write protect polarity (SD and SDIO cards only) RW 0
This bit selects the active level of the write protect input signal
(SDWP). The usage of the write protect input signal (SDWP) is
optional and depends on the system integration and the type of
the connector housing that accommodates the card.
0x0: Active high level.
0x1: Active low level.
7 CDP Card detect polarity (All cards) RW 0
This bit selects the active level of the card detect input signal
(SDCD). The usage of the card detect input signal (SDCD) is
optional and depends on the system integration and the type of
the connector housing that accommodates the card.
0x0: Active high level.
0x1: Active low level.
3432 MMC/SD/SDIO Card Interface SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated