Texas Instruments OMAP36 Series, Техническое справочное руководство

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SCM Functional Description
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Table 13-8. PBIAS Cell and Extended-Drain I/O Pin Bit Controls (continued)
Control Signals for PBIAS0 Control Signals for PBIAS1 Description
and/or and/or
Associated Extended-Drain Associated Extended-Drain
I/O Cell I/O Cell
Software must keep the PBIASLITEPWRDNZ0/
PBIASLITEPWRDNZ1 signal to 0b0 whenever the
SDMMC1_VDDS/SIM_VDDS signal is ramping. When this bit is
set to 0, the PAD is floating.
PBIASLITEPWRDNZ0 GPIO_IO_PWRDNZ The same PBIASLITEPWRDNZ0 bit that controls power-down
mode for the PBIAS0 cell is also used to control power-down
mode for its associated MMC1 extended-drain I/O cell (see
Figure 13-12).
A second extended-drain I/O cell (associated GPIO pads) does
not share the same power-down control with the PBIAS1 cell, as
the MMC/SD/SDIO1 I/O cell does with the PBIAS0 cell. A
separate power-down control, GPIO_IO_PWRDNZ, which
resides in a different register
(CONTROL.
CONTROL_WKUP_CTRL ) is used to power it down.
(See Figure 13-12 )
PBIASLITEVMODE0 PBIASLITEVMODE1 Bit that controls SDMMC1_VDDS / SIM_VDDS voltage level.
Default state of this bit is HIGH, indicating SDMMC1_VDDS/
SIM_VDDS = 3.0 V)
PBIASLITESUPPLYHIGH0 PBIASLITESUPPLYHIGH1 Bit that describes whether the SDMMC1_VDDS/SIM_VDDS
supply is 3.0 V or 1.8 V
PRG_SDMMC1_SPEEDCTRL - Bit that controls the extended-drain MMC1 I/O cell speed.
The control is in the CONTROL. CONTROL_PROG_IO1 register.
The second extended-drain I/O cell (GPIO pads associated)
does not have speed control.
PBIASLITEVMODEERROR0 PBIASLITEVMODEERROR1 Status indicating whether the software-programmed VMODE
level matches the SUPPLY_HI output signal
PBIAS0_ERROR PBIAS1_ERROR This signal determines whether the software-programmed
PBIASLITVMODEx level matches PBIASLITESUPPLYHIGHx
This signal is generated only when PBIASLITEVMODEENx is
high.
Table 13-9 lists the power supplies for the PBIAS and the extended-drain I/O cells.
Table 13-9. Power Supplies
Name Description
VDD2 Core voltage supply
SDMMC1_VDDS or SIM_VDDS (vdds_sdmmc1 or vdds_sim I/O supply voltage nominal 1.8 V/ 3.0 V
power pins of the device)
VDDS 1.8-V supply for the input buffer
13.4.5.1 PBIAS Cells
The PBIAS0 cell provides a bias for the extended-drain I/O cell used with high voltage for the
MMC/SD/SDIO1 interface.
NOTE: With the appropriate configuration of the PBIAS0 cell, the gpio_120 through gpio_125 I/Os
(MuxMode = 0x4) can operate in 3-V mode.
The PBIAS1 cell provides a bias for a second extended-drain I/O cell.
NOTE: With the appropriate PBIAS1 cell configuration, the gpio_126, gpio_127, and gpio_129 I/Os
(MuxMode = 0x4) can operate in 3-V mode.
2468 System Control Module SWPU177N – December 2009 – Revised November 2010
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