Texas Instruments OMAP36 Series, Техническое справочное руководство

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VIDSIZEY [10:0]
VIDORGSIZEY [10:0]
VIDFIRVINC [12:0] 1024 x
=
dss-E093
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VIDSIZEX
[10:0]
VIDORGSIZEX [10:0]
VIDFIRHINC [12:0] 1024
=
x
dss-E094
Public Version
Display Subsystem Basic Programming Model
www.ti.com
7.5.3.3.4 Video Up-/Down-Sampling Configuration
The video horizontal up/downsampling block for video pipeline n (with n = 1 or 2) is enabled/disabled by
setting/resetting the DSS.
DISPC_VIDn_ATTRIBUTES [5] VIDRESIZEENABLE bit.
The video vertical up/downsampling block for video pipeline n is enabled/disabled by setting/resetting the
DSS.
DISPC_VIDn_ATTRIBUTES [6] VIDRESIZEENABLE bit.
Set a valid configuration before enabling the video up/downsampling block.
NOTE: Vertical and horizontal downsampling are limited to a 1/4 resize factor.
After a register change, either the DSS. DISPC_CONTROL [6] GODIGITAL or DSS. DISPC_CONTROL [5]
GOLCD bit must be set. The software must wait until the hardware resets this bit before setting it. The
software reset is not recommended because the application cannot ensure that the bit is reset before the
hardware reset.
The following fields define the configuration of the video up/downsampling block for video pipeline n:
• Vertical up/downsampling increment value (DSS. DISPC_VIDn_FIR [27:16] VIDFIRVINC bit field, with n
= 1 or 2): The unsigned integer value range is [1:4096]. The software calculates the value using the
following equation:
(10)
NOTE:
• If the VIDFIRVINC[11:0] bit field value is greater than 4096, it is clipped to 4096. If
VIDSIZEY[10:0] equals 0x1, VIDSIZEY[10:0] is replaced by 0x2 in the previous
equation.
• The VIDORGSIZEY[10:0] and VIDSIZEY[10:0] bit field values must be programmed with
the value desired minus 1.
• Horizontal up/downsampling increment value (DSS. DISPC_VIDn_FIR [11:0] VIDFIRHINC bit field, with
n = 1 or 2): The unsigned integer value range is [1:4096]. The software calculates the value using the
following equation:
(11)
NOTE:
• If the VIDFIRHINC[11:0] bit field value is greater than 4096, it is clipped to 4096. If
VIDSIZEX[10:0] equals 1, VIDSIZEX[10:0] is replaced by 2 in the previous equation.
• The VIDORGSIZEX[10:0] and VIDSIZEX[10:0] bit field values must be programmed with
the value desired minus 1.
• Vertical up/downsampling accumulator value (DSS. DISPC_VIDn_ACCUl [25:16] VIDVERTICALACCU
bit field): The unsigned integer value range is [0:1023]. The accumulator value indicates in which
phase the vertical filtering starts. The value 0 indicates that 0 is the first phase used by the hardware to
generate the first data (see
Table 7-48 ).
• Vertical up/downsampling line buffer configuration (DSS. DISPC_VIDn_ATTRIBUTES [22]
VIDLINEBUFFERSPLIT bit): The default value at reset time is 0x0 (line buffers are not split). The
backward compatibility is maintained versus OMAP2420 and OMAP2430 devices. When the bit field is
set, each line buffer is split into two line buffers to be able to use six line buffers instead of three.
• Vertical up/downsampling line buffer configuration (DSS. DISPC_VIDn_ATTRIBUTES [21]
VIDVERTICALTAPS bit): The default value at reset time is 0x0 (3-tap configuration is used). If the bit
field is reset, the 3-tap configuration is used. The backward compatibility is maintained versus
OMAP2420 and OMAP2430 devices. When the bit field is set, the 5-tap configuration is used and the
1716 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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