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PRCM Register Manual
Bits Field Name Description Type Reset
21 EN_MCSPI4 McSPI 4 functional clock control. RW 0x0
0x0: McSPI 4 functional clock is disabled
0x1: McSPI 4 functional clock is enabled
20 EN_MCSPI3 McSPI 3 functional clock control. RW 0x0
0x0: McSPI 3 functional clock is disabled
0x1: McSPI 3 functional clock is enabled
19 EN_MCSPI2 McSPI 2 functional clock control. RW 0x0
0x0: McSPI 2 functional clock is disabled
0x1: McSPI 2 functional clock is enabled
18 EN_MCSPI1 McSPI 1 functional clock control. RW 0x0
0x0: McSPI 1 functional clock is disabled
0x1: McSPI 1 functional clock is enabled
17 EN_I2C3 I2C 3 functional clock control. RW 0x0
0x0: I2C 3 functional clock is disabled
0x1: I2C 3 functional clock is enabled
16 EN_I2C2 I2C 2 functional clock control. RW 0x0
0x0: I2C 2 functional clock is disabled
0x1: I2C 2 functional clock is enabled
15 EN_I2C1 I2C 1 functional clock control. RW 0x0
0x0: I2C 1 functional clock is disabled
0x1: I2C 1 functional clock is enabled
14 EN_UART2 UART 2 functional clock control. RW 0x0
0x0: UART 2 functional clock is disabled
0x1: UART 2 functional clock is enabled
13 EN_UART1 UART 1 functional clock control. RW 0x0
0x0: UART 1 functional clock is disabled
0x1: UART 1 functional clock is enabled
12 EN_GPT11 GPTIMER 11 functional clock control. RW 0x0
0x0: GPTIMER 11 functional clock is disabled
0x1: GPTIMER 11 functional clock is enabled
11 EN_GPT10 GPTIMER 10 functional clock control. RW 0x0
0x0: GPTIMER 10 functional clock is disabled
0x1: GPTIMER 10 functional clock is enabled
10 EN_MCBSP5 McBSP 5 functional clock control. RW 0x0
0x0: McBSP 5 functional clock is disabled
0x1: McBSP 5 functional clock is enabled
9 EN_MCBSP1 McBSP 1 functional clock control. RW 0x0
0x0: McBSP 1 functional clock is disabled
0x1: McBSP 1 functional clock is enabled
8:1 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00
0 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0
Table 3-139. Register Call Summary for Register CM_FCLKEN1_CORE
PRCM Functional Description
• CORE Power Domain Clock Controls : [0] [1] [2] [3] [4] [5] [6] [7]
PRCM Basic Programming Model
• CM_FCLKEN_ <domain_name> (Functional Clock Enable Register) : [8]
PRCM Register Manual
• CORE_CM Register Summary : [9]
475 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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