Texas Instruments OMAP36 Series, Техническое справочное руководство

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HS I
2
C Integration
NOTE: The I2Ci. I2C_CON [15] I2C_EN bit can hold the functional clock domain of the HS I
2
C
controller in reset after the device reset has been released. When the system bus reset is
removed, this bit remains cleared. The functional part of the I
2
C controller is held in reset
state while this bit is 0, and all configuration registers can be accessed.
The I2Ci. I2C_CON [15] I2C_EN bit must be set to 1 to enable the functional part of the I
2
C
controller.
The I2Ci. I2C_SYSS [0] RDONE bit is asserted only after the module is enabled by setting the
I2Ci. I2C_CON [15] I2C_EN bit to 1.
17.3.1.4 HS I
2
C Power Domain
The three HS I
2
C controllers are connected to the CORE power domain, whereas the HS I2C4 controller
belongs to the WKUP power domain.
17.3.2 HS I
2
C Hardware Requests
17.3.2.1 HS I
2
C DMA Requests
Each HS I
2
C controller can generate two DMA requests to the system DMA (sDMA) controller. Table 17-7
lists the DMA requests with mapping on the sDMA controller.
Table 17-7. HS I
2
C DMA Requests
Name Source Destination Description
(sDMA controller)
I2C1_DMA_TX I2C1 S_DMA_26 I2C1 DMA write request to inform the sDMA to write new data in the
I2C1.
I2C_DATA [7:0] register
I2C1_DMA_RX I2C1 S_DMA_27 I2C1 DMA read request to inform the sDMA to read the data in the
I2C1.
I2C_DATA [7:0] register
I2C2_DMA_TX I2C2 S_DMA_28 I2C2 DMA write request to inform the sDMA to write new data in the
I2C2.
I2C_DATA [7:0] register
I2C2_DMA_RX I2C2 S_DMA_29 I2C2 DMA read request to inform the sDMA to read the data in the
I2C2.
I2C_DATA [7:0] register
I2C3_DMA_TX I2C3 S_DMA_24 I2C3 DMA write request to inform the sDMA to write new data in the
I2C3.
I2C_DATA [7:0] register
I2C3_DMA_RX I2C3 S_DMA_25 I2C3 DMA read request to inform the sDMA to read the data in the
I2C3.
I2C_DATA [7:0] register
NOTE: The HS I
2
C4 does not generate any DMA request.
17.3.2.2 HS I
2
C Interrupt Requests
Each HS I
2
C controller can generate an interrupt I2Ci_IRQ to the MPU subsystem. Table 17-8 lists the
interrupt requests with the mapping on the MPU interrupt controller (INTC).
Table 17-8. HS I
2
C Interrupt Requests
Name Source Destination (MPU INTC)
I2C1_IRQ I2C1 M_IRQ_56
I2C2_IRQ I2C2 M_IRQ_57
I2C3_IRQ I2C3 M_IRQ_61
An event can generate an interrupt request when the corresponding mask bit in the I2Ci. I2C_IE register is
set to 1. Table 17-9 summarizes the events causing the generation of an interrupt request.
2787 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
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