Texas Instruments OMAP36 Series, Техническое справочное руководство

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L3 Interconnect
Table 9-30. L3_SI_FLAG_STATUS_1 for Debug Error (continued)
Flag Bit Number Source Flag Bit Number Source
Agent Error Agent Error
11 43
12 44
13 45
14 46
15 47
16 48
17 49
18 50
19 51
20 52
21 53
22 54
23 Reserved 55 Reserved
24 56
25 57
26 58
27 59
28 60
29 61
30 62
31 63
9.2.4 L3 Interconnect Basic Programming Model
9.2.4.1 General Recommendation
The L3 interconnect registers must be read or written with little-endian attributes; otherwise, the result is
undefined.
CAUTION
Overlapping between protection regions with the same priority level leads to
unpredictable behavior and must be avoided.
9.2.4.2 Initialization
At the release of power on reset, the L3 firewall default configuration enables all accesses to target
modules, except for a section of the OCM ROM.
Generally, software must configure the firewall properly to avoid poor use of the hardware resources.
L3 time-out capabilities are also disabled at reset.
9.2.4.3 Error Analysis
The information required to analyze an error source is logged in several registers (see Table 9-26 ). The
number of registers to access depends on the error source. When investigating the origin of an error,
software reads a set of error log registers. At each stage, the register either states the current error or
points to the next agent in which the error is logged.
Figure 9-10 shows the software sequence required in
most cases.
2021 SWPU177N – December 2009 – Revised November 2010 Interconnect
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